51 lines
2.5 KiB
Markdown
51 lines
2.5 KiB
Markdown
# EzLogic
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## Problem
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Our task is to reverse engineer a flag checker implemented on an **FPGA**.The hardware system is constructed from a **netlist** synthesized by Xilinx Vivado, where the netlist serves a role similar to assembly language in the software domain, representing a lower-level, more hardware-specific description. The netlist is described using **Verilog**, enabling convenient simulation of the system.
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## Knowledge
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If you find yourself new to Verilog or digital integrated circuit design, that's completely fine. We're here to help with a recommended Verilog syntax tutorial and an official manual covering all the foundational components used in the netlist.
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- Verilog Syntax: https://www.chipverify.com/tutorials/verilog
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- FPGA Design Elements: https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/Design-Elements
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## Simulation
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For system simulation, you can choose one of the following tools:
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- [Xilinx Vivado](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html) (free version is enough)
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- [Icarus Verilog](https://github.com/steveicarus/iverilog) and [gtkwave](http://gtkwave.sourceforge.net/) (open-source software)
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### Using Vivado
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1. Install Vivado HL WebPACK version (must select Zynq 7000 series boards support)
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2. Create a project (just click "next" to the end, nothing is needed to configure)
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3. In "sources" window, add the Verilog files (*.v) to **simulation sources**
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4. Run simulation (run until stops)
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5. Watch the value of signal `success` or check the output message in "Tcl Console"
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### Using Icarus Verilog
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1. Installing iverilog and gtkwave
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```
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sudo apt-get install iverilog gtkwave
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```
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2. Compilation
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Note: Zynq 7000 FPGA primitives (FDCE, LUT, ...) are not supported by iverilog, so behavioral models for these components are provided for simulation purposes.
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```
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iverilog -s EzLogic_tb -o EzLogic.vvp ./problem/EzLogic_top_synth.v ./problem/EzLogic_tb.v ./behavioral\ models/*.v
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```
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If successful, you can see `EzLogic.vvp` file in the folder.
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3. Running the Simulation
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```
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vvp EzLogic.vvp
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```
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The results of the check are printed on the terminal.
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4. Viewing in Graph Form
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If you want to check internal signals, just use gtkwave.
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```
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gtkwave EzLogic.vcd
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```
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## Hints
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- A schematic printout is included in `schematic` folder, which can greatly assist you in understanding the data pathways and program logic. (Only for EzLogic)
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- Variable names are auto-generated by Vivado Synthesizer and don't necessarily mean anything; don't be confused by the names.
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