271 lines
7.5 KiB
Verilog
271 lines
7.5 KiB
Verilog
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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// Date : Sat Aug 31 17:14:12 2024
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// Host : DESKTOP-9V3OCBF running 64-bit major release (build 9200)
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// Command : write_verilog -force EzLogic_top_synth.v
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// Design : EzLogic_top
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// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
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// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
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// design files.
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// Device : xc7z010iclg225-1L
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// --------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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(* STRUCTURAL_NETLIST = "yes" *)
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module EzLogic_top
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(clk,
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rst_n,
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data_in,
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valid_in,
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data_out,
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valid_out);
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input clk;
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input rst_n;
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input [7:0]data_in;
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input valid_in;
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output [7:0]data_out;
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output valid_out;
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wire \<const0> ;
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wire \<const1> ;
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wire clk;
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wire clk_IBUF;
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wire clk_IBUF_BUFG;
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wire [7:0]data_in;
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wire [7:0]data_in_IBUF;
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wire [7:0]data_out;
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wire [7:0]data_out_OBUF;
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wire \data_reg[3]_i_2_n_0 ;
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wire \data_reg[3]_i_3_n_0 ;
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wire \data_reg[3]_i_4_n_0 ;
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wire \data_reg[3]_i_5_n_0 ;
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wire \data_reg[7]_i_2_n_0 ;
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wire \data_reg[7]_i_3_n_0 ;
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wire \data_reg[7]_i_4_n_0 ;
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wire \data_reg[7]_i_5_n_0 ;
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wire \data_reg[7]_i_6_n_0 ;
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wire \data_reg_reg[3]_i_1_n_0 ;
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wire \data_reg_reg[3]_i_1_n_1 ;
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wire \data_reg_reg[3]_i_1_n_2 ;
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wire \data_reg_reg[3]_i_1_n_3 ;
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wire \data_reg_reg[7]_i_1_n_1 ;
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wire \data_reg_reg[7]_i_1_n_2 ;
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wire \data_reg_reg[7]_i_1_n_3 ;
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wire [7:0]p_0_in;
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wire rst_n;
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wire rst_n_IBUF;
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wire valid_in;
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wire valid_in_IBUF;
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wire valid_out;
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wire valid_out_OBUF;
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GND GND
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(.G(\<const0> ));
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VCC VCC
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(.P(\<const1> ));
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BUFG clk_IBUF_BUFG_inst
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(.I(clk_IBUF),
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.O(clk_IBUF_BUFG));
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IBUF clk_IBUF_inst
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(.I(clk),
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.O(clk_IBUF));
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IBUF \data_in_IBUF[0]_inst
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(.I(data_in[0]),
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.O(data_in_IBUF[0]));
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IBUF \data_in_IBUF[1]_inst
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(.I(data_in[1]),
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.O(data_in_IBUF[1]));
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IBUF \data_in_IBUF[2]_inst
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(.I(data_in[2]),
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.O(data_in_IBUF[2]));
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IBUF \data_in_IBUF[3]_inst
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(.I(data_in[3]),
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.O(data_in_IBUF[3]));
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IBUF \data_in_IBUF[4]_inst
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(.I(data_in[4]),
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.O(data_in_IBUF[4]));
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IBUF \data_in_IBUF[5]_inst
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(.I(data_in[5]),
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.O(data_in_IBUF[5]));
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IBUF \data_in_IBUF[6]_inst
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(.I(data_in[6]),
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.O(data_in_IBUF[6]));
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IBUF \data_in_IBUF[7]_inst
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(.I(data_in[7]),
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.O(data_in_IBUF[7]));
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OBUF \data_out_OBUF[0]_inst
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(.I(data_out_OBUF[0]),
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.O(data_out[0]));
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OBUF \data_out_OBUF[1]_inst
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(.I(data_out_OBUF[1]),
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.O(data_out[1]));
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OBUF \data_out_OBUF[2]_inst
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(.I(data_out_OBUF[2]),
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.O(data_out[2]));
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OBUF \data_out_OBUF[3]_inst
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(.I(data_out_OBUF[3]),
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.O(data_out[3]));
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OBUF \data_out_OBUF[4]_inst
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(.I(data_out_OBUF[4]),
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.O(data_out[4])); OBUF \data_out_OBUF[5]_inst
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(.I(data_out_OBUF[5]),
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.O(data_out[5]));
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OBUF \data_out_OBUF[6]_inst
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(.I(data_out_OBUF[6]),
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.O(data_out[6]));
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OBUF \data_out_OBUF[7]_inst
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(.I(data_out_OBUF[7]),
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.O(data_out[7]));
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LUT2 #(
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.INIT(4'h6))
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\data_reg[3]_i_2
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(.I0(data_out_OBUF[5]),
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.I1(data_in_IBUF[3]),
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.O(\data_reg[3]_i_2_n_0 ));
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LUT2 #(
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.INIT(4'h6))
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\data_reg[3]_i_3
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(.I0(data_out_OBUF[6]),
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.I1(data_in_IBUF[2]),
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.O(\data_reg[3]_i_3_n_0 ));
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LUT2 #(
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.INIT(4'h6))
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\data_reg[3]_i_4
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(.I0(data_out_OBUF[2]),
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.I1(data_in_IBUF[1]),
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.O(\data_reg[3]_i_4_n_0 ));
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LUT2 #(
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.INIT(4'h6))
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\data_reg[3]_i_5
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(.I0(data_out_OBUF[4]),
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.I1(data_in_IBUF[0]),
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.O(\data_reg[3]_i_5_n_0 ));
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LUT1 #(
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.INIT(2'h1))
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\data_reg[7]_i_2
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(.I0(rst_n_IBUF),
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.O(\data_reg[7]_i_2_n_0 ));
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LUT2 #(
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.INIT(4'h6))
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\data_reg[7]_i_3
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(.I0(data_out_OBUF[7]),
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.I1(data_in_IBUF[7]),
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.O(\data_reg[7]_i_3_n_0 ));
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LUT2 #(
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.INIT(4'h6))
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\data_reg[7]_i_4
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(.I0(data_out_OBUF[0]),
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.I1(data_in_IBUF[6]),
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.O(\data_reg[7]_i_4_n_0 ));
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LUT2 #(
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.INIT(4'h6))
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\data_reg[7]_i_5
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(.I0(data_out_OBUF[3]),
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.I1(data_in_IBUF[5]),
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.O(\data_reg[7]_i_5_n_0 ));
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LUT2 #(
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.INIT(4'h6))
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\data_reg[7]_i_6
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(.I0(data_out_OBUF[1]),
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.I1(data_in_IBUF[4]),
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.O(\data_reg[7]_i_6_n_0 ));
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FDCE #(
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.INIT(1'b0))
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\data_reg_reg[0]
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(.C(clk_IBUF_BUFG),
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.CE(valid_in_IBUF),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(p_0_in[0]),
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.Q(data_out_OBUF[0]));
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FDCE #(
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.INIT(1'b0))
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\data_reg_reg[1]
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(.C(clk_IBUF_BUFG),
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.CE(valid_in_IBUF),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(p_0_in[1]),
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.Q(data_out_OBUF[1]));
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FDCE #(
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.INIT(1'b0))
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\data_reg_reg[2]
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(.C(clk_IBUF_BUFG),
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.CE(valid_in_IBUF),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(p_0_in[2]),
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.Q(data_out_OBUF[2]));
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FDCE #(
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.INIT(1'b0))
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\data_reg_reg[3]
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(.C(clk_IBUF_BUFG),
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.CE(valid_in_IBUF),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(p_0_in[3]),
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.Q(data_out_OBUF[3]));
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(* ADDER_THRESHOLD = "35" *)
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CARRY4 \data_reg_reg[3]_i_1
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(.CI(\<const0> ),
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.CO({\data_reg_reg[3]_i_1_n_0 ,\data_reg_reg[3]_i_1_n_1 ,\data_reg_reg[3]_i_1_n_2 ,\data_reg_reg[3]_i_1_n_3 }),
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.CYINIT(\<const0> ),
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.DI({data_out_OBUF[5],data_out_OBUF[6],data_out_OBUF[2],data_out_OBUF[4]}),
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.O(p_0_in[3:0]),
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.S({\data_reg[3]_i_2_n_0 ,\data_reg[3]_i_3_n_0 ,\data_reg[3]_i_4_n_0 ,\data_reg[3]_i_5_n_0 }));
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FDCE #(
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.INIT(1'b0))
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\data_reg_reg[4]
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(.C(clk_IBUF_BUFG),
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.CE(valid_in_IBUF),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(p_0_in[4]),
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.Q(data_out_OBUF[4]));
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FDCE #(
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.INIT(1'b0))
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\data_reg_reg[5]
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(.C(clk_IBUF_BUFG),
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.CE(valid_in_IBUF),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(p_0_in[5]),
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.Q(data_out_OBUF[5]));
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FDCE #(
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.INIT(1'b0))
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\data_reg_reg[6]
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(.C(clk_IBUF_BUFG),
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.CE(valid_in_IBUF),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(p_0_in[6]),
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.Q(data_out_OBUF[6]));
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FDCE #(
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.INIT(1'b0))
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\data_reg_reg[7]
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(.C(clk_IBUF_BUFG),
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.CE(valid_in_IBUF),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(p_0_in[7]),
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.Q(data_out_OBUF[7]));
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(* ADDER_THRESHOLD = "35" *)
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CARRY4 \data_reg_reg[7]_i_1
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(.CI(\data_reg_reg[3]_i_1_n_0 ),
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.CO({\data_reg_reg[7]_i_1_n_1 ,\data_reg_reg[7]_i_1_n_2 ,\data_reg_reg[7]_i_1_n_3 }),
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.CYINIT(\<const0> ),
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.DI({\<const0> ,data_out_OBUF[0],data_out_OBUF[3],data_out_OBUF[1]}),
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.O(p_0_in[7:4]),
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.S({\data_reg[7]_i_3_n_0 ,\data_reg[7]_i_4_n_0 ,\data_reg[7]_i_5_n_0 ,\data_reg[7]_i_6_n_0 }));
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IBUF rst_n_IBUF_inst
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(.I(rst_n),
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.O(rst_n_IBUF));
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IBUF valid_in_IBUF_inst
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(.I(valid_in),
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.O(valid_in_IBUF));
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OBUF valid_out_OBUF_inst
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(.I(valid_out_OBUF),
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.O(valid_out));
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FDCE #(
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.INIT(1'b0))
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valid_out_reg
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(.C(clk_IBUF_BUFG),
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.CE(\<const1> ),
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.CLR(\data_reg[7]_i_2_n_0 ),
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.D(valid_in_IBUF),
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.Q(valid_out_OBUF));
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endmodule
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