70 lines
1.5 KiB
Verilog
70 lines
1.5 KiB
Verilog
`ifdef verilator3
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`else
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`timescale 1 ps / 1 ps
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`endif
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//
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// FDCE primitive for Xilinx FPGAs
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// Compatible with Verilator tool (www.veripool.org)
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// Copyright (c) 2019-2022 Frédéric REQUIN
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// License : BSD
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//
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/* verilator coverage_off */
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module FDCE
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#(
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parameter [0:0] IS_C_INVERTED = 1'b0,
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parameter [0:0] IS_D_INVERTED = 1'b0,
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parameter [0:0] IS_CLR_INVERTED = 1'b0,
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parameter [0:0] INIT = 1'b0
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)
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(
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// Clock
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input wire C,
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// Clock enable
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input wire CE,
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// Asynchronous clear
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input wire CLR,
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// Data in
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input wire D,
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// Data out
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output wire Q
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);
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reg _r_Q;
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wire _w_CLR = CLR ^ IS_CLR_INVERTED;
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wire _w_D = D ^ IS_D_INVERTED;
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initial begin : INIT_STATE
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_r_Q = INIT[0];
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end
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generate
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if (IS_C_INVERTED) begin : GEN_CLK_NEG
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always @(negedge C or posedge _w_CLR) begin
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if (_w_CLR) begin
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_r_Q <= 1'b0;
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end
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else if (CE) begin
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_r_Q <= _w_D;
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end
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end
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end
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else begin : GEN_CLK_POS
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always @(posedge C or posedge _w_CLR) begin
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if (_w_CLR) begin
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_r_Q <= 1'b0;
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end
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else if (CE) begin
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_r_Q <= _w_D;
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end
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end
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end
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endgenerate
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assign Q = _r_Q;
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endmodule
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/* verilator coverage_on */
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