39 lines
937 B
Verilog
39 lines
937 B
Verilog
`ifdef verilator3
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`else
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`timescale 1 ps / 1 ps
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`endif
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//
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// CARRY4 primitive for Xilinx FPGAs
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// Compatible with Verilator tool (www.veripool.org)
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// Copyright (c) 2019-2022 Frédéric REQUIN
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// License : BSD
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//
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/* verilator coverage_off */
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module CARRY4
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(
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// Carry cascade input
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input wire CI,
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//
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input wire CYINIT,
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// Carry MUX data input
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input wire [3:0] DI,
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// Carry MUX select line
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input wire [3:0] S,
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// Carry out of each stage of the chain
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output wire [3:0] CO,
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// Carry chain XOR general data out
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output wire [3:0] O
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);
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wire _w_CO0 = S[0] ? CI | CYINIT : DI[0];
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wire _w_CO1 = S[1] ? _w_CO0 : DI[1];
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wire _w_CO2 = S[2] ? _w_CO1 : DI[2];
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wire _w_CO3 = S[3] ? _w_CO2 : DI[3];
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assign CO = { _w_CO3, _w_CO2, _w_CO1, _w_CO0 };
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assign O = S ^ { _w_CO2, _w_CO1, _w_CO0, CI | CYINIT };
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endmodule
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/* verilator coverage_on */
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