22 lines
361 B
Verilog
22 lines
361 B
Verilog
`ifdef verilator3
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`else
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`timescale 1 ps / 1 ps
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`endif
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//
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// BUFG primitive for Xilinx FPGAs
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// Compatible with Verilator tool (www.veripool.org)
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// Copyright (c) 2019-2022 Frédéric REQUIN
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// License : BSD
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//
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/*verilator coverage_off*/
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module BUFG
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(
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input I,
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output O /* verilator clocker */
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);
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assign O = I;
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endmodule
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/*verilator coverage_on*/ |