1405 lines
70 KiB
Plaintext
1405 lines
70 KiB
Plaintext
#! /c/Source/iverilog-install/bin/vvp
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:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 12;
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:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\system.vpi";
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:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\vhdl_sys.vpi";
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:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\vhdl_textio.vpi";
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:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\v2005_math.vpi";
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:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\va_math.vpi";
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S_000001f7f2b9eb50 .scope module, "EzLogic_tb" "EzLogic_tb" 2 3;
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.timescale -6 -7;
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P_000001f7f2ae3ad0 .param/str "FLAG_TO_TEST" 0 2 4, "o0";
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P_000001f7f2ae3b08 .param/l "N" 0 2 5, +C4<00000000000000000000000000101010>;
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v000001f7f2c1aa10_0 .var "clk", 0 0;
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v000001f7f2c1a1f0_0 .var "counter", 6 0;
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v000001f7f2c1bc30_0 .var "counter2", 6 0;
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v000001f7f2c1c630_0 .var "data_in", 7 0;
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v000001f7f2c1add0_0 .net "data_out", 7 0, L_000001f7f2c1a650; 1 drivers
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v000001f7f2c1ac90_0 .var "data_out_all", 0 335;
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L_000001f7f2c1f3c0 .functor BUFT 1, C4<001100000111100010011101010101101001001011110010111111100010001110111011001011000101110110011110000101100100000001100110010100111011011011001011001000010111110010010101001010011001100011001110000101111011011100010100001101111000100011011001010010011001010100100110100000001011010010111100111001001100001100001010100101101100011101010011>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1b550_0 .net "data_std", 0 335, L_000001f7f2c1f3c0; 1 drivers
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L_000001f7f2c1eb50 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10 .array "flag_test_arr", 41 0;
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v000001f7f2c1be10_0 .net v000001f7f2c1be10 0, 7 0, L_000001f7f2c1eb50; 1 drivers
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L_000001f7f2c1eb08 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_1 .net v000001f7f2c1be10 1, 7 0, L_000001f7f2c1eb08; 1 drivers
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L_000001f7f2c1eac0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_2 .net v000001f7f2c1be10 2, 7 0, L_000001f7f2c1eac0; 1 drivers
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L_000001f7f2c1ea78 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_3 .net v000001f7f2c1be10 3, 7 0, L_000001f7f2c1ea78; 1 drivers
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L_000001f7f2c1ea30 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_4 .net v000001f7f2c1be10 4, 7 0, L_000001f7f2c1ea30; 1 drivers
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L_000001f7f2c1e9e8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_5 .net v000001f7f2c1be10 5, 7 0, L_000001f7f2c1e9e8; 1 drivers
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L_000001f7f2c1e9a0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_6 .net v000001f7f2c1be10 6, 7 0, L_000001f7f2c1e9a0; 1 drivers
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L_000001f7f2c1e958 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_7 .net v000001f7f2c1be10 7, 7 0, L_000001f7f2c1e958; 1 drivers
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L_000001f7f2c1e910 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_8 .net v000001f7f2c1be10 8, 7 0, L_000001f7f2c1e910; 1 drivers
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L_000001f7f2c1e8c8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_9 .net v000001f7f2c1be10 9, 7 0, L_000001f7f2c1e8c8; 1 drivers
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L_000001f7f2c1e880 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_10 .net v000001f7f2c1be10 10, 7 0, L_000001f7f2c1e880; 1 drivers
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L_000001f7f2c1e838 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_11 .net v000001f7f2c1be10 11, 7 0, L_000001f7f2c1e838; 1 drivers
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L_000001f7f2c1e7f0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_12 .net v000001f7f2c1be10 12, 7 0, L_000001f7f2c1e7f0; 1 drivers
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L_000001f7f2c1e7a8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_13 .net v000001f7f2c1be10 13, 7 0, L_000001f7f2c1e7a8; 1 drivers
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L_000001f7f2c1e760 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_14 .net v000001f7f2c1be10 14, 7 0, L_000001f7f2c1e760; 1 drivers
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L_000001f7f2c1e718 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_15 .net v000001f7f2c1be10 15, 7 0, L_000001f7f2c1e718; 1 drivers
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L_000001f7f2c1e6d0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_16 .net v000001f7f2c1be10 16, 7 0, L_000001f7f2c1e6d0; 1 drivers
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L_000001f7f2c1e688 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_17 .net v000001f7f2c1be10 17, 7 0, L_000001f7f2c1e688; 1 drivers
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L_000001f7f2c1e640 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_18 .net v000001f7f2c1be10 18, 7 0, L_000001f7f2c1e640; 1 drivers
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L_000001f7f2c1e5f8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_19 .net v000001f7f2c1be10 19, 7 0, L_000001f7f2c1e5f8; 1 drivers
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L_000001f7f2c1e5b0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_20 .net v000001f7f2c1be10 20, 7 0, L_000001f7f2c1e5b0; 1 drivers
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L_000001f7f2c1e568 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_21 .net v000001f7f2c1be10 21, 7 0, L_000001f7f2c1e568; 1 drivers
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L_000001f7f2c1e520 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_22 .net v000001f7f2c1be10 22, 7 0, L_000001f7f2c1e520; 1 drivers
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L_000001f7f2c1e4d8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_23 .net v000001f7f2c1be10 23, 7 0, L_000001f7f2c1e4d8; 1 drivers
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L_000001f7f2c1e490 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_24 .net v000001f7f2c1be10 24, 7 0, L_000001f7f2c1e490; 1 drivers
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L_000001f7f2c1e448 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_25 .net v000001f7f2c1be10 25, 7 0, L_000001f7f2c1e448; 1 drivers
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L_000001f7f2c1e400 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_26 .net v000001f7f2c1be10 26, 7 0, L_000001f7f2c1e400; 1 drivers
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L_000001f7f2c1e3b8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_27 .net v000001f7f2c1be10 27, 7 0, L_000001f7f2c1e3b8; 1 drivers
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L_000001f7f2c1e370 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_28 .net v000001f7f2c1be10 28, 7 0, L_000001f7f2c1e370; 1 drivers
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L_000001f7f2c1e328 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_29 .net v000001f7f2c1be10 29, 7 0, L_000001f7f2c1e328; 1 drivers
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L_000001f7f2c1e2e0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_30 .net v000001f7f2c1be10 30, 7 0, L_000001f7f2c1e2e0; 1 drivers
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L_000001f7f2c1e298 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_31 .net v000001f7f2c1be10 31, 7 0, L_000001f7f2c1e298; 1 drivers
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L_000001f7f2c1e250 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_32 .net v000001f7f2c1be10 32, 7 0, L_000001f7f2c1e250; 1 drivers
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L_000001f7f2c1e208 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_33 .net v000001f7f2c1be10 33, 7 0, L_000001f7f2c1e208; 1 drivers
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L_000001f7f2c1e1c0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_34 .net v000001f7f2c1be10 34, 7 0, L_000001f7f2c1e1c0; 1 drivers
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L_000001f7f2c1e178 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_35 .net v000001f7f2c1be10 35, 7 0, L_000001f7f2c1e178; 1 drivers
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L_000001f7f2c1e130 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_36 .net v000001f7f2c1be10 36, 7 0, L_000001f7f2c1e130; 1 drivers
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L_000001f7f2c1e0e8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_37 .net v000001f7f2c1be10 37, 7 0, L_000001f7f2c1e0e8; 1 drivers
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L_000001f7f2c1e0a0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_38 .net v000001f7f2c1be10 38, 7 0, L_000001f7f2c1e0a0; 1 drivers
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L_000001f7f2c1e058 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_39 .net v000001f7f2c1be10 39, 7 0, L_000001f7f2c1e058; 1 drivers
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L_000001f7f2c1e010 .functor BUFT 1, C4<01101111>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_40 .net v000001f7f2c1be10 40, 7 0, L_000001f7f2c1e010; 1 drivers
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L_000001f7f2c1dfc8 .functor BUFT 1, C4<00110000>, C4<0>, C4<0>, C4<0>;
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v000001f7f2c1be10_41 .net v000001f7f2c1be10 41, 7 0, L_000001f7f2c1dfc8; 1 drivers
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v000001f7f2c1c450_0 .var "rst_n", 0 0;
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v000001f7f2c1b7d0_0 .var "start", 0 0;
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v000001f7f2c1ae70_0 .net "success", 0 0, L_000001f7f2c67c20; 1 drivers
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v000001f7f2c1b5f0_0 .var "valid_in", 0 0;
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v000001f7f2c1b190_0 .net "valid_out", 0 0, L_000001f7f2c6f520; 1 drivers
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E_000001f7f2b95b20 .event posedge, v000001f7f2b98740_0;
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E_000001f7f2b95560 .event negedge, v000001f7f2c1b7d0_0;
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L_000001f7f2c67c20 .cmp/eq 336, L_000001f7f2c1f3c0, v000001f7f2c1ac90_0;
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S_000001f7f2ba25e0 .scope generate, "genblk1[0]" "genblk1[0]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b95be0 .param/l "i" 0 2 22, +C4<00>;
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S_000001f7f2ba3720 .scope generate, "genblk1[1]" "genblk1[1]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b957e0 .param/l "i" 0 2 22, +C4<01>;
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S_000001f7f2b218a0 .scope generate, "genblk1[2]" "genblk1[2]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b96120 .param/l "i" 0 2 22, +C4<010>;
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S_000001f7f2b21a30 .scope generate, "genblk1[3]" "genblk1[3]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b95d20 .param/l "i" 0 2 22, +C4<011>;
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S_000001f7f2b20410 .scope generate, "genblk1[4]" "genblk1[4]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b95f20 .param/l "i" 0 2 22, +C4<0100>;
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S_000001f7f2b205a0 .scope generate, "genblk1[5]" "genblk1[5]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b96420 .param/l "i" 0 2 22, +C4<0101>;
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S_000001f7f2b1a660 .scope generate, "genblk1[6]" "genblk1[6]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b95ea0 .param/l "i" 0 2 22, +C4<0110>;
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S_000001f7f2b1a7f0 .scope generate, "genblk1[7]" "genblk1[7]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b96060 .param/l "i" 0 2 22, +C4<0111>;
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S_000001f7f2b191d0 .scope generate, "genblk1[8]" "genblk1[8]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b95ee0 .param/l "i" 0 2 22, +C4<01000>;
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S_000001f7f2b19360 .scope generate, "genblk1[9]" "genblk1[9]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b96360 .param/l "i" 0 2 22, +C4<01001>;
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S_000001f7f2b13d20 .scope generate, "genblk1[10]" "genblk1[10]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b96220 .param/l "i" 0 2 22, +C4<01010>;
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S_000001f7f2b13eb0 .scope generate, "genblk1[11]" "genblk1[11]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b955a0 .param/l "i" 0 2 22, +C4<01011>;
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S_000001f7f2b133e0 .scope generate, "genblk1[12]" "genblk1[12]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b963a0 .param/l "i" 0 2 22, +C4<01100>;
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S_000001f7f2b13570 .scope generate, "genblk1[13]" "genblk1[13]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b92560 .param/l "i" 0 2 22, +C4<01101>;
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S_000001f7f2b12eb0 .scope generate, "genblk1[14]" "genblk1[14]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b92720 .param/l "i" 0 2 22, +C4<01110>;
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S_000001f7f2b13040 .scope generate, "genblk1[15]" "genblk1[15]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b92aa0 .param/l "i" 0 2 22, +C4<01111>;
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S_000001f7f2ba4670 .scope generate, "genblk1[16]" "genblk1[16]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b92f60 .param/l "i" 0 2 22, +C4<010000>;
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S_000001f7f2ba3ea0 .scope generate, "genblk1[17]" "genblk1[17]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b92be0 .param/l "i" 0 2 22, +C4<010001>;
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S_000001f7f2ba4030 .scope generate, "genblk1[18]" "genblk1[18]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b926e0 .param/l "i" 0 2 22, +C4<010010>;
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S_000001f7f2ba41c0 .scope generate, "genblk1[19]" "genblk1[19]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b92760 .param/l "i" 0 2 22, +C4<010011>;
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S_000001f7f2ba4350 .scope generate, "genblk1[20]" "genblk1[20]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b929e0 .param/l "i" 0 2 22, +C4<010100>;
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S_000001f7f2ba4b20 .scope generate, "genblk1[21]" "genblk1[21]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b92d20 .param/l "i" 0 2 22, +C4<010101>;
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S_000001f7f2ba4990 .scope generate, "genblk1[22]" "genblk1[22]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b93320 .param/l "i" 0 2 22, +C4<010110>;
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S_000001f7f2ba44e0 .scope generate, "genblk1[23]" "genblk1[23]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b927a0 .param/l "i" 0 2 22, +C4<010111>;
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S_000001f7f2ba4800 .scope generate, "genblk1[24]" "genblk1[24]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b931a0 .param/l "i" 0 2 22, +C4<011000>;
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S_000001f7f2ba4cb0 .scope generate, "genblk1[25]" "genblk1[25]" 2 22, 2 22 0, S_000001f7f2b9eb50;
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.timescale -6 -7;
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P_000001f7f2b92ae0 .param/l "i" 0 2 22, +C4<011001>;
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S_000001f7f2ba5360 .scope generate, "genblk1[26]" "genblk1[26]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b933e0 .param/l "i" 0 2 22, +C4<011010>;
|
|
S_000001f7f2ba67b0 .scope generate, "genblk1[27]" "genblk1[27]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b93160 .param/l "i" 0 2 22, +C4<011011>;
|
|
S_000001f7f2ba5fe0 .scope generate, "genblk1[28]" "genblk1[28]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b933a0 .param/l "i" 0 2 22, +C4<011100>;
|
|
S_000001f7f2ba5810 .scope generate, "genblk1[29]" "genblk1[29]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b931e0 .param/l "i" 0 2 22, +C4<011101>;
|
|
S_000001f7f2ba59a0 .scope generate, "genblk1[30]" "genblk1[30]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b93360 .param/l "i" 0 2 22, +C4<011110>;
|
|
S_000001f7f2ba5cc0 .scope generate, "genblk1[31]" "genblk1[31]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92e60 .param/l "i" 0 2 22, +C4<011111>;
|
|
S_000001f7f2ba6940 .scope generate, "genblk1[32]" "genblk1[32]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92b20 .param/l "i" 0 2 22, +C4<0100000>;
|
|
S_000001f7f2ba54f0 .scope generate, "genblk1[33]" "genblk1[33]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92620 .param/l "i" 0 2 22, +C4<0100001>;
|
|
S_000001f7f2ba6620 .scope generate, "genblk1[34]" "genblk1[34]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92820 .param/l "i" 0 2 22, +C4<0100010>;
|
|
S_000001f7f2ba5680 .scope generate, "genblk1[35]" "genblk1[35]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b929a0 .param/l "i" 0 2 22, +C4<0100011>;
|
|
S_000001f7f2ba4eb0 .scope generate, "genblk1[36]" "genblk1[36]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92b60 .param/l "i" 0 2 22, +C4<0100100>;
|
|
S_000001f7f2ba5040 .scope generate, "genblk1[37]" "genblk1[37]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92660 .param/l "i" 0 2 22, +C4<0100101>;
|
|
S_000001f7f2ba5e50 .scope generate, "genblk1[38]" "genblk1[38]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b93120 .param/l "i" 0 2 22, +C4<0100110>;
|
|
S_000001f7f2ba51d0 .scope generate, "genblk1[39]" "genblk1[39]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92e20 .param/l "i" 0 2 22, +C4<0100111>;
|
|
S_000001f7f2ba6170 .scope generate, "genblk1[40]" "genblk1[40]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92fa0 .param/l "i" 0 2 22, +C4<0101000>;
|
|
S_000001f7f2ba6ad0 .scope generate, "genblk1[41]" "genblk1[41]" 2 22, 2 22 0, S_000001f7f2b9eb50;
|
|
.timescale -6 -7;
|
|
P_000001f7f2b92860 .param/l "i" 0 2 22, +C4<0101001>;
|
|
S_000001f7f2ba6300 .scope module, "inst" "EzLogic_top" 2 27, 3 16 0, S_000001f7f2b9eb50;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "clk";
|
|
.port_info 1 /INPUT 1 "rst_n";
|
|
.port_info 2 /INPUT 8 "data_in";
|
|
.port_info 3 /INPUT 1 "valid_in";
|
|
.port_info 4 /OUTPUT 8 "data_out";
|
|
.port_info 5 /OUTPUT 1 "valid_out";
|
|
L_000001f7f2c1eb98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c192b0_0 .net "<const0>", 0 0, L_000001f7f2c1eb98; 1 drivers
|
|
L_000001f7f2c1ebe0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c19850_0 .net "<const1>", 0 0, L_000001f7f2c1ebe0; 1 drivers
|
|
v000001f7f2c19a30_0 .net *"_ivl_115", 0 0, L_000001f7f2c6ae20; 1 drivers
|
|
v000001f7f2c19ad0_0 .net *"_ivl_117", 0 0, L_000001f7f2c69840; 1 drivers
|
|
v000001f7f2c19c10_0 .net *"_ivl_119", 0 0, L_000001f7f2c6a2e0; 1 drivers
|
|
v000001f7f2c18630_0 .net *"_ivl_121", 0 0, L_000001f7f2c6a380; 1 drivers
|
|
v000001f7f2c18d10_0 .net *"_ivl_151", 0 0, L_000001f7f2c69f20; 1 drivers
|
|
v000001f7f2c18db0_0 .net *"_ivl_153", 0 0, L_000001f7f2c6a880; 1 drivers
|
|
v000001f7f2c18e50_0 .net *"_ivl_155", 0 0, L_000001f7f2c6a9c0; 1 drivers
|
|
v000001f7f2c18ef0_0 .net *"_ivl_160", 2 0, L_000001f7f2c68da0; 1 drivers
|
|
v000001f7f2c18f90_0 .net "clk", 0 0, v000001f7f2c1aa10_0; 1 drivers
|
|
v000001f7f2c19030_0 .net "clk_IBUF", 0 0, L_000001f7f2b86510; 1 drivers
|
|
v000001f7f2c190d0_0 .net "clk_IBUF_BUFG", 0 0, L_000001f7f2b864a0; 1 drivers
|
|
v000001f7f2c19170_0 .net "data_in", 7 0, v000001f7f2c1c630_0; 1 drivers
|
|
v000001f7f2c19210_0 .net "data_in_IBUF", 7 0, L_000001f7f2c1b730; 1 drivers
|
|
v000001f7f2c193f0_0 .net "data_out", 7 0, L_000001f7f2c1a650; alias, 1 drivers
|
|
v000001f7f2c19490_0 .net "data_out_OBUF", 7 0, L_000001f7f2c69a20; 1 drivers
|
|
v000001f7f2c1a8d0_0 .net "data_reg[3]_i_2_n_0", 0 0, L_000001f7f2c1c1d0; 1 drivers
|
|
v000001f7f2c1c310_0 .net "data_reg[3]_i_3_n_0", 0 0, L_000001f7f2c1b690; 1 drivers
|
|
v000001f7f2c1c3b0_0 .net "data_reg[3]_i_4_n_0", 0 0, L_000001f7f2c1bf50; 1 drivers
|
|
v000001f7f2c1b910_0 .net "data_reg[3]_i_5_n_0", 0 0, L_000001f7f2c1d530; 1 drivers
|
|
v000001f7f2c1afb0_0 .net "data_reg[7]_i_2_n_0", 0 0, L_000001f7f2c1c9f0; 1 drivers
|
|
v000001f7f2c1a970_0 .net "data_reg[7]_i_3_n_0", 0 0, L_000001f7f2c1d170; 1 drivers
|
|
v000001f7f2c1a830_0 .net "data_reg[7]_i_4_n_0", 0 0, L_000001f7f2c1d210; 1 drivers
|
|
v000001f7f2c1a5b0_0 .net "data_reg[7]_i_5_n_0", 0 0, L_000001f7f2c1cdb0; 1 drivers
|
|
v000001f7f2c1aab0_0 .net "data_reg[7]_i_6_n_0", 0 0, L_000001f7f2c1c810; 1 drivers
|
|
v000001f7f2c1b870_0 .net "data_reg_reg[3]_i_1_n_0", 0 0, L_000001f7f2c69c00; 1 drivers
|
|
v000001f7f2c1ad30_0 .net "data_reg_reg[3]_i_1_n_1", 0 0, L_000001f7f2c6ac40; 1 drivers
|
|
v000001f7f2c1ab50_0 .net "data_reg_reg[3]_i_1_n_2", 0 0, L_000001f7f2c6ad80; 1 drivers
|
|
v000001f7f2c1c770_0 .net "data_reg_reg[3]_i_1_n_3", 0 0, L_000001f7f2c69ac0; 1 drivers
|
|
v000001f7f2c1c270_0 .net "data_reg_reg[7]_i_1_n_1", 0 0, L_000001f7f2c67680; 1 drivers
|
|
v000001f7f2c1a010_0 .net "data_reg_reg[7]_i_1_n_2", 0 0, L_000001f7f2c67900; 1 drivers
|
|
v000001f7f2c1a790_0 .net "data_reg_reg[7]_i_1_n_3", 0 0, L_000001f7f2c67860; 1 drivers
|
|
v000001f7f2c1a150_0 .net "p_0_in", 7 0, L_000001f7f2c67fe0; 1 drivers
|
|
v000001f7f2c1c6d0_0 .net "rst_n", 0 0, v000001f7f2c1c450_0; 1 drivers
|
|
v000001f7f2c1b9b0_0 .net "rst_n_IBUF", 0 0, L_000001f7f2c6f440; 1 drivers
|
|
v000001f7f2c1b050_0 .net "valid_in", 0 0, v000001f7f2c1b5f0_0; 1 drivers
|
|
v000001f7f2c1abf0_0 .net "valid_in_IBUF", 0 0, L_000001f7f2c6fb40; 1 drivers
|
|
v000001f7f2c1b0f0_0 .net "valid_out", 0 0, L_000001f7f2c6f520; alias, 1 drivers
|
|
v000001f7f2c1b2d0_0 .net "valid_out_OBUF", 0 0, v000001f7f2c183b0_0; 1 drivers
|
|
L_000001f7f2c1bb90 .part v000001f7f2c1c630_0, 0, 1;
|
|
L_000001f7f2c1af10 .part v000001f7f2c1c630_0, 1, 1;
|
|
L_000001f7f2c1a330 .part v000001f7f2c1c630_0, 2, 1;
|
|
L_000001f7f2c1b230 .part v000001f7f2c1c630_0, 3, 1;
|
|
L_000001f7f2c1c590 .part v000001f7f2c1c630_0, 4, 1;
|
|
L_000001f7f2c1a0b0 .part v000001f7f2c1c630_0, 5, 1;
|
|
L_000001f7f2c1bff0 .part v000001f7f2c1c630_0, 6, 1;
|
|
L_000001f7f2c1ba50 .part v000001f7f2c1c630_0, 7, 1;
|
|
LS_000001f7f2c1b730_0_0 .concat8 [ 1 1 1 1], L_000001f7f2b866d0, L_000001f7f2b86970, L_000001f7f2b86580, L_000001f7f2b87000;
|
|
LS_000001f7f2c1b730_0_4 .concat8 [ 1 1 1 1], L_000001f7f2b87230, L_000001f7f2b865f0, L_000001f7f2b86740, L_000001f7f2b867b0;
|
|
L_000001f7f2c1b730 .concat8 [ 4 4 0 0], LS_000001f7f2c1b730_0_0, LS_000001f7f2c1b730_0_4;
|
|
L_000001f7f2c1b370 .part L_000001f7f2c69a20, 0, 1;
|
|
L_000001f7f2c1baf0 .part L_000001f7f2c69a20, 1, 1;
|
|
L_000001f7f2c1c090 .part L_000001f7f2c69a20, 2, 1;
|
|
L_000001f7f2c1a290 .part L_000001f7f2c69a20, 3, 1;
|
|
L_000001f7f2c1a3d0 .part L_000001f7f2c69a20, 4, 1;
|
|
L_000001f7f2c1a470 .part L_000001f7f2c69a20, 5, 1;
|
|
L_000001f7f2c1bcd0 .part L_000001f7f2c69a20, 6, 1;
|
|
L_000001f7f2c1c130 .part L_000001f7f2c69a20, 7, 1;
|
|
LS_000001f7f2c1a650_0_0 .concat8 [ 1 1 1 1], L_000001f7f2b86890, L_000001f7f2c66e90, L_000001f7f2c66020, L_000001f7f2c66330;
|
|
LS_000001f7f2c1a650_0_4 .concat8 [ 1 1 1 1], L_000001f7f2c66cd0, L_000001f7f2c663a0, L_000001f7f2c66870, L_000001f7f2c66f00;
|
|
L_000001f7f2c1a650 .concat8 [ 4 4 0 0], LS_000001f7f2c1a650_0_0, LS_000001f7f2c1a650_0_4;
|
|
L_000001f7f2c1c4f0 .part L_000001f7f2c69a20, 5, 1;
|
|
L_000001f7f2c1b410 .part L_000001f7f2c1b730, 3, 1;
|
|
L_000001f7f2c1beb0 .part L_000001f7f2c69a20, 6, 1;
|
|
L_000001f7f2c1a6f0 .part L_000001f7f2c1b730, 2, 1;
|
|
L_000001f7f2c1d670 .part L_000001f7f2c69a20, 2, 1;
|
|
L_000001f7f2c1d0d0 .part L_000001f7f2c1b730, 1, 1;
|
|
L_000001f7f2c1de90 .part L_000001f7f2c69a20, 4, 1;
|
|
L_000001f7f2c1dc10 .part L_000001f7f2c1b730, 0, 1;
|
|
L_000001f7f2c1d2b0 .part L_000001f7f2c69a20, 7, 1;
|
|
L_000001f7f2c1d5d0 .part L_000001f7f2c1b730, 7, 1;
|
|
L_000001f7f2c1d850 .part L_000001f7f2c69a20, 0, 1;
|
|
L_000001f7f2c1dd50 .part L_000001f7f2c1b730, 6, 1;
|
|
L_000001f7f2c1d8f0 .part L_000001f7f2c69a20, 3, 1;
|
|
L_000001f7f2c1cb30 .part L_000001f7f2c1b730, 5, 1;
|
|
L_000001f7f2c1d030 .part L_000001f7f2c69a20, 1, 1;
|
|
L_000001f7f2c1c950 .part L_000001f7f2c1b730, 4, 1;
|
|
L_000001f7f2c1ce50 .part L_000001f7f2c67fe0, 0, 1;
|
|
L_000001f7f2c1ca90 .part L_000001f7f2c67fe0, 1, 1;
|
|
L_000001f7f2c1d7b0 .part L_000001f7f2c67fe0, 2, 1;
|
|
L_000001f7f2c1cbd0 .part L_000001f7f2c67fe0, 3, 1;
|
|
L_000001f7f2c6ae20 .part L_000001f7f2c69a20, 5, 1;
|
|
L_000001f7f2c69840 .part L_000001f7f2c69a20, 6, 1;
|
|
L_000001f7f2c6a2e0 .part L_000001f7f2c69a20, 2, 1;
|
|
L_000001f7f2c6a380 .part L_000001f7f2c69a20, 4, 1;
|
|
L_000001f7f2c698e0 .concat [ 1 1 1 1], L_000001f7f2c6a380, L_000001f7f2c6a2e0, L_000001f7f2c69840, L_000001f7f2c6ae20;
|
|
L_000001f7f2c6a100 .concat [ 1 1 1 1], L_000001f7f2c1d530, L_000001f7f2c1bf50, L_000001f7f2c1b690, L_000001f7f2c1c1d0;
|
|
L_000001f7f2c69c00 .part L_000001f7f2c6a4c0, 3, 1;
|
|
L_000001f7f2c6ac40 .part L_000001f7f2c6a4c0, 2, 1;
|
|
L_000001f7f2c6ad80 .part L_000001f7f2c6a4c0, 1, 1;
|
|
L_000001f7f2c69ac0 .part L_000001f7f2c6a4c0, 0, 1;
|
|
L_000001f7f2c69fc0 .part L_000001f7f2c67fe0, 4, 1;
|
|
L_000001f7f2c69980 .part L_000001f7f2c67fe0, 5, 1;
|
|
L_000001f7f2c6a740 .part L_000001f7f2c67fe0, 6, 1;
|
|
L_000001f7f2c6a240 .part L_000001f7f2c67fe0, 7, 1;
|
|
LS_000001f7f2c69a20_0_0 .concat8 [ 1 1 1 1], v000001f7f2c13320_0, v000001f7f2c13b40_0, v000001f7f2c12ba0_0, v000001f7f2c129c0_0;
|
|
LS_000001f7f2c69a20_0_4 .concat8 [ 1 1 1 1], v000001f7f2c15b50_0, v000001f7f2c14250_0, v000001f7f2c14430_0, v000001f7f2c15510_0;
|
|
L_000001f7f2c69a20 .concat8 [ 4 4 0 0], LS_000001f7f2c69a20_0_0, LS_000001f7f2c69a20_0_4;
|
|
L_000001f7f2c69f20 .part L_000001f7f2c69a20, 0, 1;
|
|
L_000001f7f2c6a880 .part L_000001f7f2c69a20, 3, 1;
|
|
L_000001f7f2c6a9c0 .part L_000001f7f2c69a20, 1, 1;
|
|
L_000001f7f2c6aba0 .concat [ 1 1 1 1], L_000001f7f2c6a9c0, L_000001f7f2c6a880, L_000001f7f2c69f20, L_000001f7f2c1eb98;
|
|
L_000001f7f2c677c0 .concat [ 1 1 1 1], L_000001f7f2c1c810, L_000001f7f2c1cdb0, L_000001f7f2c1d210, L_000001f7f2c1d170;
|
|
L_000001f7f2c67680 .part L_000001f7f2c68da0, 2, 1;
|
|
L_000001f7f2c67900 .part L_000001f7f2c68da0, 1, 1;
|
|
L_000001f7f2c67860 .part L_000001f7f2c68da0, 0, 1;
|
|
L_000001f7f2c68da0 .part L_000001f7f2c6aa60, 0, 3;
|
|
L_000001f7f2c67fe0 .concat8 [ 4 4 0 0], L_000001f7f2c666b0, L_000001f7f2c6fde0;
|
|
S_000001f7f2ba5b30 .scope module, "GND" "GND" 3 63, 4 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /OUTPUT 1 "G";
|
|
v000001f7f2b99960_0 .net "G", 0 0, L_000001f7f2c1eb98; alias, 1 drivers
|
|
S_000001f7f2ba6c60 .scope module, "VCC" "VCC" 3 65, 5 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /OUTPUT 1 "P";
|
|
v000001f7f2b99c80_0 .net "P", 0 0, L_000001f7f2c1ebe0; alias, 1 drivers
|
|
S_000001f7f2ba6490 .scope module, "clk_IBUF_BUFG_inst" "BUFG" 3 67, 6 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b864a0 .functor BUFZ 1, L_000001f7f2b86510, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b98b00_0 .net "I", 0 0, L_000001f7f2b86510; alias, 1 drivers
|
|
v000001f7f2b9a180_0 .net "O", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
S_000001f7f2c08d90 .scope module, "clk_IBUF_inst" "IBUF" 3 70, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b86510 .functor BUFZ 1, v000001f7f2c1aa10_0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b98740_0 .net "I", 0 0, v000001f7f2c1aa10_0; alias, 1 drivers
|
|
v000001f7f2b98c40_0 .net "O", 0 0, L_000001f7f2b86510; alias, 1 drivers
|
|
S_000001f7f2c082a0 .scope module, "data_in_IBUF[0]_inst" "IBUF" 3 73, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b866d0 .functor BUFZ 1, L_000001f7f2c1bb90, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b99460_0 .net "I", 0 0, L_000001f7f2c1bb90; 1 drivers
|
|
v000001f7f2b99aa0_0 .net "O", 0 0, L_000001f7f2b866d0; 1 drivers
|
|
S_000001f7f2c08750 .scope module, "data_in_IBUF[1]_inst" "IBUF" 3 76, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b86970 .functor BUFZ 1, L_000001f7f2c1af10, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b990a0_0 .net "I", 0 0, L_000001f7f2c1af10; 1 drivers
|
|
v000001f7f2b99a00_0 .net "O", 0 0, L_000001f7f2b86970; 1 drivers
|
|
S_000001f7f2c09240 .scope module, "data_in_IBUF[2]_inst" "IBUF" 3 79, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b86580 .functor BUFZ 1, L_000001f7f2c1a330, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b9a2c0_0 .net "I", 0 0, L_000001f7f2c1a330; 1 drivers
|
|
v000001f7f2b99780_0 .net "O", 0 0, L_000001f7f2b86580; 1 drivers
|
|
S_000001f7f2c088e0 .scope module, "data_in_IBUF[3]_inst" "IBUF" 3 82, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b87000 .functor BUFZ 1, L_000001f7f2c1b230, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b98a60_0 .net "I", 0 0, L_000001f7f2c1b230; 1 drivers
|
|
v000001f7f2b99140_0 .net "O", 0 0, L_000001f7f2b87000; 1 drivers
|
|
S_000001f7f2c09560 .scope module, "data_in_IBUF[4]_inst" "IBUF" 3 85, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b87230 .functor BUFZ 1, L_000001f7f2c1c590, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b989c0_0 .net "I", 0 0, L_000001f7f2c1c590; 1 drivers
|
|
v000001f7f2b99fa0_0 .net "O", 0 0, L_000001f7f2b87230; 1 drivers
|
|
S_000001f7f2c090b0 .scope module, "data_in_IBUF[5]_inst" "IBUF" 3 88, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b865f0 .functor BUFZ 1, L_000001f7f2c1a0b0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b986a0_0 .net "I", 0 0, L_000001f7f2c1a0b0; 1 drivers
|
|
v000001f7f2b9a220_0 .net "O", 0 0, L_000001f7f2b865f0; 1 drivers
|
|
S_000001f7f2c093d0 .scope module, "data_in_IBUF[6]_inst" "IBUF" 3 91, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b86740 .functor BUFZ 1, L_000001f7f2c1bff0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b98ce0_0 .net "I", 0 0, L_000001f7f2c1bff0; 1 drivers
|
|
v000001f7f2b98560_0 .net "O", 0 0, L_000001f7f2b86740; 1 drivers
|
|
S_000001f7f2c096f0 .scope module, "data_in_IBUF[7]_inst" "IBUF" 3 94, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b867b0 .functor BUFZ 1, L_000001f7f2c1ba50, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b98920_0 .net "I", 0 0, L_000001f7f2c1ba50; 1 drivers
|
|
v000001f7f2b98e20_0 .net "O", 0 0, L_000001f7f2b867b0; 1 drivers
|
|
S_000001f7f2c08f20 .scope module, "data_out_OBUF[0]_inst" "OBUF" 3 97, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2b86890 .functor BUFZ 1, L_000001f7f2c1b370, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b99000_0 .net "I", 0 0, L_000001f7f2c1b370; 1 drivers
|
|
v000001f7f2b996e0_0 .net "O", 0 0, L_000001f7f2b86890; 1 drivers
|
|
S_000001f7f2c09a10 .scope module, "data_out_OBUF[1]_inst" "OBUF" 3 100, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c66e90 .functor BUFZ 1, L_000001f7f2c1baf0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b98d80_0 .net "I", 0 0, L_000001f7f2c1baf0; 1 drivers
|
|
v000001f7f2b98ec0_0 .net "O", 0 0, L_000001f7f2c66e90; 1 drivers
|
|
S_000001f7f2c09880 .scope module, "data_out_OBUF[2]_inst" "OBUF" 3 103, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c66020 .functor BUFZ 1, L_000001f7f2c1c090, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b99dc0_0 .net "I", 0 0, L_000001f7f2c1c090; 1 drivers
|
|
v000001f7f2b9a0e0_0 .net "O", 0 0, L_000001f7f2c66020; 1 drivers
|
|
S_000001f7f2c09ba0 .scope module, "data_out_OBUF[3]_inst" "OBUF" 3 106, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c66330 .functor BUFZ 1, L_000001f7f2c1a290, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b991e0_0 .net "I", 0 0, L_000001f7f2c1a290; 1 drivers
|
|
v000001f7f2b9a360_0 .net "O", 0 0, L_000001f7f2c66330; 1 drivers
|
|
S_000001f7f2c08110 .scope module, "data_out_OBUF[4]_inst" "OBUF" 3 109, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c66cd0 .functor BUFZ 1, L_000001f7f2c1a3d0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b99280_0 .net "I", 0 0, L_000001f7f2c1a3d0; 1 drivers
|
|
v000001f7f2b99320_0 .net "O", 0 0, L_000001f7f2c66cd0; 1 drivers
|
|
S_000001f7f2c08a70 .scope module, "data_out_OBUF[5]_inst" "OBUF" 3 111, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c663a0 .functor BUFZ 1, L_000001f7f2c1a470, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b99500_0 .net "I", 0 0, L_000001f7f2c1a470; 1 drivers
|
|
v000001f7f2b995a0_0 .net "O", 0 0, L_000001f7f2c663a0; 1 drivers
|
|
S_000001f7f2c09d30 .scope module, "data_out_OBUF[6]_inst" "OBUF" 3 114, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c66870 .functor BUFZ 1, L_000001f7f2c1bcd0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2b99640_0 .net "I", 0 0, L_000001f7f2c1bcd0; 1 drivers
|
|
v000001f7f2b86070_0 .net "O", 0 0, L_000001f7f2c66870; 1 drivers
|
|
S_000001f7f2c07f80 .scope module, "data_out_OBUF[7]_inst" "OBUF" 3 117, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c66f00 .functor BUFZ 1, L_000001f7f2c1c130, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0b1b0_0 .net "I", 0 0, L_000001f7f2c1c130; 1 drivers
|
|
v000001f7f2c0bc50_0 .net "O", 0 0, L_000001f7f2c66f00; 1 drivers
|
|
S_000001f7f2c08430 .scope module, "data_reg[3]_i_2" "LUT2" 3 122, 9 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /INPUT 1 "I1";
|
|
.port_info 2 /OUTPUT 1 "O";
|
|
P_000001f7f2b92c60 .param/l "INIT" 0 9 15, C4<0110>;
|
|
v000001f7f2c0bb10_0 .net "I0", 0 0, L_000001f7f2c1c4f0; 1 drivers
|
|
v000001f7f2c0b2f0_0 .net "I1", 0 0, L_000001f7f2c1b410; 1 drivers
|
|
v000001f7f2c0b610_0 .net "O", 0 0, L_000001f7f2c1c1d0; alias, 1 drivers
|
|
L_000001f7f2c1ec28 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0b6b0_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ec28; 1 drivers
|
|
v000001f7f2c0bbb0_0 .net "_w_idx", 1 0, L_000001f7f2c1a510; 1 drivers
|
|
L_000001f7f2c1a510 .concat [ 1 1 0 0], L_000001f7f2c1c4f0, L_000001f7f2c1b410;
|
|
L_000001f7f2c1c1d0 .part/v L_000001f7f2c1ec28, L_000001f7f2c1a510, 1;
|
|
S_000001f7f2c08c00 .scope module, "data_reg[3]_i_3" "LUT2" 3 128, 9 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /INPUT 1 "I1";
|
|
.port_info 2 /OUTPUT 1 "O";
|
|
P_000001f7f2b934a0 .param/l "INIT" 0 9 15, C4<0110>;
|
|
v000001f7f2c0be30_0 .net "I0", 0 0, L_000001f7f2c1beb0; 1 drivers
|
|
v000001f7f2c09f90_0 .net "I1", 0 0, L_000001f7f2c1a6f0; 1 drivers
|
|
v000001f7f2c0bcf0_0 .net "O", 0 0, L_000001f7f2c1b690; alias, 1 drivers
|
|
L_000001f7f2c1ec70 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0b750_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ec70; 1 drivers
|
|
v000001f7f2c0a170_0 .net "_w_idx", 1 0, L_000001f7f2c1b4b0; 1 drivers
|
|
L_000001f7f2c1b4b0 .concat [ 1 1 0 0], L_000001f7f2c1beb0, L_000001f7f2c1a6f0;
|
|
L_000001f7f2c1b690 .part/v L_000001f7f2c1ec70, L_000001f7f2c1b4b0, 1;
|
|
S_000001f7f2c085c0 .scope module, "data_reg[3]_i_4" "LUT2" 3 134, 9 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /INPUT 1 "I1";
|
|
.port_info 2 /OUTPUT 1 "O";
|
|
P_000001f7f2b93220 .param/l "INIT" 0 9 15, C4<0110>;
|
|
v000001f7f2c0ac10_0 .net "I0", 0 0, L_000001f7f2c1d670; 1 drivers
|
|
v000001f7f2c0a670_0 .net "I1", 0 0, L_000001f7f2c1d0d0; 1 drivers
|
|
v000001f7f2c0a030_0 .net "O", 0 0, L_000001f7f2c1bf50; alias, 1 drivers
|
|
L_000001f7f2c1ecb8 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0b390_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ecb8; 1 drivers
|
|
v000001f7f2c0b890_0 .net "_w_idx", 1 0, L_000001f7f2c1bd70; 1 drivers
|
|
L_000001f7f2c1bd70 .concat [ 1 1 0 0], L_000001f7f2c1d670, L_000001f7f2c1d0d0;
|
|
L_000001f7f2c1bf50 .part/v L_000001f7f2c1ecb8, L_000001f7f2c1bd70, 1;
|
|
S_000001f7f2c10460 .scope module, "data_reg[3]_i_5" "LUT2" 3 140, 9 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /INPUT 1 "I1";
|
|
.port_info 2 /OUTPUT 1 "O";
|
|
P_000001f7f2b926a0 .param/l "INIT" 0 9 15, C4<0110>;
|
|
v000001f7f2c0a2b0_0 .net "I0", 0 0, L_000001f7f2c1de90; 1 drivers
|
|
v000001f7f2c0aa30_0 .net "I1", 0 0, L_000001f7f2c1dc10; 1 drivers
|
|
v000001f7f2c0af30_0 .net "O", 0 0, L_000001f7f2c1d530; alias, 1 drivers
|
|
L_000001f7f2c1ed00 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0bd90_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ed00; 1 drivers
|
|
v000001f7f2c0b7f0_0 .net "_w_idx", 1 0, L_000001f7f2c1cc70; 1 drivers
|
|
L_000001f7f2c1cc70 .concat [ 1 1 0 0], L_000001f7f2c1de90, L_000001f7f2c1dc10;
|
|
L_000001f7f2c1d530 .part/v L_000001f7f2c1ed00, L_000001f7f2c1cc70, 1;
|
|
S_000001f7f2c118b0 .scope module, "data_reg[7]_i_2" "LUT1" 3 146, 10 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
P_000001f7f2b930a0 .param/l "INIT" 0 10 15, C4<01>;
|
|
v000001f7f2c0ae90_0 .net "I0", 0 0, L_000001f7f2c6f440; alias, 1 drivers
|
|
v000001f7f2c0a710_0 .net "O", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
L_000001f7f2c1ed48 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0a990_0 .net/2u *"_ivl_0", 1 0, L_000001f7f2c1ed48; 1 drivers
|
|
L_000001f7f2c1c9f0 .part/v L_000001f7f2c1ed48, L_000001f7f2c6f440, 1;
|
|
S_000001f7f2c110e0 .scope module, "data_reg[7]_i_3" "LUT2" 3 151, 9 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /INPUT 1 "I1";
|
|
.port_info 2 /OUTPUT 1 "O";
|
|
P_000001f7f2b93060 .param/l "INIT" 0 9 15, C4<0110>;
|
|
v000001f7f2c0ba70_0 .net "I0", 0 0, L_000001f7f2c1d2b0; 1 drivers
|
|
v000001f7f2c0a3f0_0 .net "I1", 0 0, L_000001f7f2c1d5d0; 1 drivers
|
|
v000001f7f2c0a0d0_0 .net "O", 0 0, L_000001f7f2c1d170; alias, 1 drivers
|
|
L_000001f7f2c1ed90 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0a530_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ed90; 1 drivers
|
|
v000001f7f2c0b250_0 .net "_w_idx", 1 0, L_000001f7f2c1c8b0; 1 drivers
|
|
L_000001f7f2c1c8b0 .concat [ 1 1 0 0], L_000001f7f2c1d2b0, L_000001f7f2c1d5d0;
|
|
L_000001f7f2c1d170 .part/v L_000001f7f2c1ed90, L_000001f7f2c1c8b0, 1;
|
|
S_000001f7f2c0ffb0 .scope module, "data_reg[7]_i_4" "LUT2" 3 157, 9 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /INPUT 1 "I1";
|
|
.port_info 2 /OUTPUT 1 "O";
|
|
P_000001f7f2b93260 .param/l "INIT" 0 9 15, C4<0110>;
|
|
v000001f7f2c0a210_0 .net "I0", 0 0, L_000001f7f2c1d850; 1 drivers
|
|
v000001f7f2c0a350_0 .net "I1", 0 0, L_000001f7f2c1dd50; 1 drivers
|
|
v000001f7f2c0a490_0 .net "O", 0 0, L_000001f7f2c1d210; alias, 1 drivers
|
|
L_000001f7f2c1edd8 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0b930_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1edd8; 1 drivers
|
|
v000001f7f2c0aad0_0 .net "_w_idx", 1 0, L_000001f7f2c1dcb0; 1 drivers
|
|
L_000001f7f2c1dcb0 .concat [ 1 1 0 0], L_000001f7f2c1d850, L_000001f7f2c1dd50;
|
|
L_000001f7f2c1d210 .part/v L_000001f7f2c1edd8, L_000001f7f2c1dcb0, 1;
|
|
S_000001f7f2c11400 .scope module, "data_reg[7]_i_5" "LUT2" 3 163, 9 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /INPUT 1 "I1";
|
|
.port_info 2 /OUTPUT 1 "O";
|
|
P_000001f7f2b92ca0 .param/l "INIT" 0 9 15, C4<0110>;
|
|
v000001f7f2c0a5d0_0 .net "I0", 0 0, L_000001f7f2c1d8f0; 1 drivers
|
|
v000001f7f2c0b9d0_0 .net "I1", 0 0, L_000001f7f2c1cb30; 1 drivers
|
|
v000001f7f2c0a7b0_0 .net "O", 0 0, L_000001f7f2c1cdb0; alias, 1 drivers
|
|
L_000001f7f2c1ee20 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0b110_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ee20; 1 drivers
|
|
v000001f7f2c0ad50_0 .net "_w_idx", 1 0, L_000001f7f2c1ddf0; 1 drivers
|
|
L_000001f7f2c1ddf0 .concat [ 1 1 0 0], L_000001f7f2c1d8f0, L_000001f7f2c1cb30;
|
|
L_000001f7f2c1cdb0 .part/v L_000001f7f2c1ee20, L_000001f7f2c1ddf0, 1;
|
|
S_000001f7f2c11bd0 .scope module, "data_reg[7]_i_6" "LUT2" 3 169, 9 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I0";
|
|
.port_info 1 /INPUT 1 "I1";
|
|
.port_info 2 /OUTPUT 1 "O";
|
|
P_000001f7f2b92d60 .param/l "INIT" 0 9 15, C4<0110>;
|
|
v000001f7f2c0ab70_0 .net "I0", 0 0, L_000001f7f2c1d030; 1 drivers
|
|
v000001f7f2c0a850_0 .net "I1", 0 0, L_000001f7f2c1c950; 1 drivers
|
|
v000001f7f2c0a8f0_0 .net "O", 0 0, L_000001f7f2c1c810; alias, 1 drivers
|
|
L_000001f7f2c1ee68 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c0acb0_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ee68; 1 drivers
|
|
v000001f7f2c0b570_0 .net "_w_idx", 1 0, L_000001f7f2c1d710; 1 drivers
|
|
L_000001f7f2c1d710 .concat [ 1 1 0 0], L_000001f7f2c1d030, L_000001f7f2c1c950;
|
|
L_000001f7f2c1c810 .part/v L_000001f7f2c1ee68, L_000001f7f2c1d710, 1;
|
|
S_000001f7f2c11590 .scope module, "data_reg_reg[0]" "FDCE" 3 175, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2ba38b0 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2ba38e8 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2ba3920 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2ba3958 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1eeb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66b80 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1eeb0, C4<0>, C4<0>;
|
|
L_000001f7f2c1eef8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66d40 .functor XOR 1, L_000001f7f2c1ce50, L_000001f7f2c1eef8, C4<0>, C4<0>;
|
|
v000001f7f2c0adf0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c0b430_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c0afd0_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c0b070_0 .net "D", 0 0, L_000001f7f2c1ce50; 1 drivers
|
|
v000001f7f2c0b4d0_0 .net "Q", 0 0, v000001f7f2c13320_0; 1 drivers
|
|
v000001f7f2c13be0_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1eeb0; 1 drivers
|
|
v000001f7f2c133c0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1eef8; 1 drivers
|
|
v000001f7f2c13320_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c12100_0 .net "_w_CLR", 0 0, L_000001f7f2c66b80; 1 drivers
|
|
v000001f7f2c13280_0 .net "_w_D", 0 0, L_000001f7f2c66d40; 1 drivers
|
|
S_000001f7f2c10140 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c11590;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b92de0 .event posedge, v000001f7f2c12100_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c10780 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c11590;
|
|
.timescale -12 -12;
|
|
S_000001f7f2c11270 .scope module, "data_reg_reg[1]" "FDCE" 3 183, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2b131d0 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2b13208 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2b13240 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2b13278 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1ef40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66410 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1ef40, C4<0>, C4<0>;
|
|
L_000001f7f2c1ef88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66480 .functor XOR 1, L_000001f7f2c1ca90, L_000001f7f2c1ef88, C4<0>, C4<0>;
|
|
v000001f7f2c121a0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c12240_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c13d20_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c12740_0 .net "D", 0 0, L_000001f7f2c1ca90; 1 drivers
|
|
v000001f7f2c131e0_0 .net "Q", 0 0, v000001f7f2c13b40_0; 1 drivers
|
|
v000001f7f2c12f60_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1ef40; 1 drivers
|
|
v000001f7f2c13780_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1ef88; 1 drivers
|
|
v000001f7f2c13b40_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c13dc0_0 .net "_w_CLR", 0 0, L_000001f7f2c66410; 1 drivers
|
|
v000001f7f2c13000_0 .net "_w_D", 0 0, L_000001f7f2c66480; 1 drivers
|
|
S_000001f7f2c10c30 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c11270;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b92ee0 .event posedge, v000001f7f2c13dc0_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c11720 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c11270;
|
|
.timescale -12 -12;
|
|
S_000001f7f2c10f50 .scope module, "data_reg_reg[2]" "FDCE" 3 191, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2b13700 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2b13738 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2b13770 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2b137a8 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1efd0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66560 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1efd0, C4<0>, C4<0>;
|
|
L_000001f7f2c1f018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66250 .functor XOR 1, L_000001f7f2c1d7b0, L_000001f7f2c1f018, C4<0>, C4<0>;
|
|
v000001f7f2c138c0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c12d80_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c12e20_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c12ec0_0 .net "D", 0 0, L_000001f7f2c1d7b0; 1 drivers
|
|
v000001f7f2c13e60_0 .net "Q", 0 0, v000001f7f2c12ba0_0; 1 drivers
|
|
v000001f7f2c13c80_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1efd0; 1 drivers
|
|
v000001f7f2c12a60_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f018; 1 drivers
|
|
v000001f7f2c12ba0_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c13960_0 .net "_w_CLR", 0 0, L_000001f7f2c66560; 1 drivers
|
|
v000001f7f2c13a00_0 .net "_w_D", 0 0, L_000001f7f2c66250; 1 drivers
|
|
S_000001f7f2c102d0 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c10f50;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b930e0 .event posedge, v000001f7f2c13960_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c10aa0 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c10f50;
|
|
.timescale -12 -12;
|
|
S_000001f7f2c10910 .scope module, "data_reg_reg[3]" "FDCE" 3 199, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2b14040 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2b14078 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2b140b0 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2b140e8 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1f060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66c60 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f060, C4<0>, C4<0>;
|
|
L_000001f7f2c1f0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66aa0 .functor XOR 1, L_000001f7f2c1cbd0, L_000001f7f2c1f0a8, C4<0>, C4<0>;
|
|
v000001f7f2c11fc0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c12060_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c122e0_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c12380_0 .net "D", 0 0, L_000001f7f2c1cbd0; 1 drivers
|
|
v000001f7f2c12420_0 .net "Q", 0 0, v000001f7f2c129c0_0; 1 drivers
|
|
v000001f7f2c130a0_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f060; 1 drivers
|
|
v000001f7f2c136e0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f0a8; 1 drivers
|
|
v000001f7f2c129c0_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c12c40_0 .net "_w_CLR", 0 0, L_000001f7f2c66c60; 1 drivers
|
|
v000001f7f2c124c0_0 .net "_w_D", 0 0, L_000001f7f2c66aa0; 1 drivers
|
|
S_000001f7f2c11a40 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c10910;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b94020 .event posedge, v000001f7f2c12c40_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c10dc0 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c10910;
|
|
.timescale -12 -12;
|
|
S_000001f7f2c105f0 .scope module, "data_reg_reg[3]_i_1" "CARRY4" 3 206, 12 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "CI";
|
|
.port_info 1 /INPUT 1 "CYINIT";
|
|
.port_info 2 /INPUT 4 "DI";
|
|
.port_info 3 /INPUT 4 "S";
|
|
.port_info 4 /OUTPUT 4 "CO";
|
|
.port_info 5 /OUTPUT 4 "O";
|
|
L_000001f7f2c665d0 .functor OR 1, L_000001f7f2c1eb98, L_000001f7f2c1eb98, C4<0>, C4<0>;
|
|
L_000001f7f2c66640 .functor OR 1, L_000001f7f2c1eb98, L_000001f7f2c1eb98, C4<0>, C4<0>;
|
|
L_000001f7f2c666b0 .functor XOR 4, L_000001f7f2c6a100, L_000001f7f2c6a060, C4<0000>, C4<0000>;
|
|
v000001f7f2c12560_0 .net "CI", 0 0, L_000001f7f2c1eb98; alias, 1 drivers
|
|
v000001f7f2c13140_0 .net "CO", 3 0, L_000001f7f2c6a4c0; 1 drivers
|
|
v000001f7f2c12600_0 .net "CYINIT", 0 0, L_000001f7f2c1eb98; alias, 1 drivers
|
|
v000001f7f2c126a0_0 .net "DI", 3 0, L_000001f7f2c698e0; 1 drivers
|
|
v000001f7f2c13460_0 .net "O", 3 0, L_000001f7f2c666b0; 1 drivers
|
|
v000001f7f2c13820_0 .net "S", 3 0, L_000001f7f2c6a100; 1 drivers
|
|
v000001f7f2c127e0_0 .net *"_ivl_1", 0 0, L_000001f7f2c1cd10; 1 drivers
|
|
v000001f7f2c135a0_0 .net *"_ivl_11", 0 0, L_000001f7f2c1d3f0; 1 drivers
|
|
v000001f7f2c13500_0 .net *"_ivl_15", 0 0, L_000001f7f2c1d490; 1 drivers
|
|
v000001f7f2c12880_0 .net *"_ivl_17", 0 0, L_000001f7f2c1da30; 1 drivers
|
|
v000001f7f2c13aa0_0 .net *"_ivl_2", 0 0, L_000001f7f2c665d0; 1 drivers
|
|
v000001f7f2c13640_0 .net *"_ivl_21", 0 0, L_000001f7f2c1db70; 1 drivers
|
|
v000001f7f2c12b00_0 .net *"_ivl_23", 0 0, L_000001f7f2c69ca0; 1 drivers
|
|
v000001f7f2c12920_0 .net *"_ivl_28", 0 0, L_000001f7f2c66640; 1 drivers
|
|
v000001f7f2c12ce0_0 .net *"_ivl_30", 3 0, L_000001f7f2c6a060; 1 drivers
|
|
v000001f7f2c15650_0 .net *"_ivl_5", 0 0, L_000001f7f2c1cef0; 1 drivers
|
|
v000001f7f2c14750_0 .net *"_ivl_9", 0 0, L_000001f7f2c1d350; 1 drivers
|
|
v000001f7f2c15d30_0 .net "_w_CO0", 0 0, L_000001f7f2c1cf90; 1 drivers
|
|
v000001f7f2c15970_0 .net "_w_CO1", 0 0, L_000001f7f2c1d990; 1 drivers
|
|
v000001f7f2c15790_0 .net "_w_CO2", 0 0, L_000001f7f2c1dad0; 1 drivers
|
|
v000001f7f2c151f0_0 .net "_w_CO3", 0 0, L_000001f7f2c6ace0; 1 drivers
|
|
L_000001f7f2c1cd10 .part L_000001f7f2c6a100, 0, 1;
|
|
L_000001f7f2c1cef0 .part L_000001f7f2c698e0, 0, 1;
|
|
L_000001f7f2c1cf90 .functor MUXZ 1, L_000001f7f2c1cef0, L_000001f7f2c665d0, L_000001f7f2c1cd10, C4<>;
|
|
L_000001f7f2c1d350 .part L_000001f7f2c6a100, 1, 1;
|
|
L_000001f7f2c1d3f0 .part L_000001f7f2c698e0, 1, 1;
|
|
L_000001f7f2c1d990 .functor MUXZ 1, L_000001f7f2c1d3f0, L_000001f7f2c1cf90, L_000001f7f2c1d350, C4<>;
|
|
L_000001f7f2c1d490 .part L_000001f7f2c6a100, 2, 1;
|
|
L_000001f7f2c1da30 .part L_000001f7f2c698e0, 2, 1;
|
|
L_000001f7f2c1dad0 .functor MUXZ 1, L_000001f7f2c1da30, L_000001f7f2c1d990, L_000001f7f2c1d490, C4<>;
|
|
L_000001f7f2c1db70 .part L_000001f7f2c6a100, 3, 1;
|
|
L_000001f7f2c69ca0 .part L_000001f7f2c698e0, 3, 1;
|
|
L_000001f7f2c6ace0 .functor MUXZ 1, L_000001f7f2c69ca0, L_000001f7f2c1dad0, L_000001f7f2c1db70, C4<>;
|
|
L_000001f7f2c6a4c0 .concat [ 1 1 1 1], L_000001f7f2c1cf90, L_000001f7f2c1d990, L_000001f7f2c1dad0, L_000001f7f2c6ace0;
|
|
L_000001f7f2c6a060 .concat [ 1 1 1 1], L_000001f7f2c66640, L_000001f7f2c1cf90, L_000001f7f2c1d990, L_000001f7f2c1dad0;
|
|
S_000001f7f2c11d60 .scope module, "data_reg_reg[4]" "FDCE" 3 215, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2b194f0 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2b19528 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2b19560 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2b19598 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1f0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66720 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f0f0, C4<0>, C4<0>;
|
|
L_000001f7f2c1f138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66e20 .functor XOR 1, L_000001f7f2c69fc0, L_000001f7f2c1f138, C4<0>, C4<0>;
|
|
v000001f7f2c15dd0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c156f0_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c15290_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c15bf0_0 .net "D", 0 0, L_000001f7f2c69fc0; 1 drivers
|
|
v000001f7f2c14110_0 .net "Q", 0 0, v000001f7f2c15b50_0; 1 drivers
|
|
v000001f7f2c14930_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f0f0; 1 drivers
|
|
v000001f7f2c14cf0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f138; 1 drivers
|
|
v000001f7f2c15b50_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c15830_0 .net "_w_CLR", 0 0, L_000001f7f2c66720; 1 drivers
|
|
v000001f7f2c13fd0_0 .net "_w_D", 0 0, L_000001f7f2c66e20; 1 drivers
|
|
S_000001f7f2c16ad0 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c11d60;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b93ea0 .event posedge, v000001f7f2c15830_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c16940 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c11d60;
|
|
.timescale -12 -12;
|
|
S_000001f7f2c16c60 .scope module, "data_reg_reg[5]" "FDCE" 3 223, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2b1a980 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2b1a9b8 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2b1a9f0 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2b1aa28 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1f180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66db0 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f180, C4<0>, C4<0>;
|
|
L_000001f7f2c1f1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c669c0 .functor XOR 1, L_000001f7f2c69980, L_000001f7f2c1f1c8, C4<0>, C4<0>;
|
|
v000001f7f2c15a10_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c15ab0_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c153d0_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c15e70_0 .net "D", 0 0, L_000001f7f2c69980; 1 drivers
|
|
v000001f7f2c146b0_0 .net "Q", 0 0, v000001f7f2c14250_0; 1 drivers
|
|
v000001f7f2c141b0_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f180; 1 drivers
|
|
v000001f7f2c15c90_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f1c8; 1 drivers
|
|
v000001f7f2c14250_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c142f0_0 .net "_w_CLR", 0 0, L_000001f7f2c66db0; 1 drivers
|
|
v000001f7f2c155b0_0 .net "_w_D", 0 0, L_000001f7f2c669c0; 1 drivers
|
|
S_000001f7f2c16490 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c16c60;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b943e0 .event posedge, v000001f7f2c142f0_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c16300 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c16c60;
|
|
.timescale -12 -12;
|
|
S_000001f7f2c17430 .scope module, "data_reg_reg[6]" "FDCE" 3 231, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2b20730 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2b20768 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2b207a0 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2b207d8 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1f210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c668e0 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f210, C4<0>, C4<0>;
|
|
L_000001f7f2c1f258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66090 .functor XOR 1, L_000001f7f2c6a740, L_000001f7f2c1f258, C4<0>, C4<0>;
|
|
v000001f7f2c149d0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c158d0_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c14390_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c14c50_0 .net "D", 0 0, L_000001f7f2c6a740; 1 drivers
|
|
v000001f7f2c15330_0 .net "Q", 0 0, v000001f7f2c14430_0; 1 drivers
|
|
v000001f7f2c14070_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f210; 1 drivers
|
|
v000001f7f2c14ed0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f258; 1 drivers
|
|
v000001f7f2c14430_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c15470_0 .net "_w_CLR", 0 0, L_000001f7f2c668e0; 1 drivers
|
|
v000001f7f2c147f0_0 .net "_w_D", 0 0, L_000001f7f2c66090; 1 drivers
|
|
S_000001f7f2c17d90 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c17430;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b93da0 .event posedge, v000001f7f2c15470_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c178e0 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c17430;
|
|
.timescale -12 -12;
|
|
S_000001f7f2c175c0 .scope module, "data_reg_reg[7]" "FDCE" 3 239, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2b21bc0 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2b21bf8 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2b21c30 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2b21c68 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1f2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66bf0 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f2a0, C4<0>, C4<0>;
|
|
L_000001f7f2c1f2e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c66100 .functor XOR 1, L_000001f7f2c6a240, L_000001f7f2c1f2e8, C4<0>, C4<0>;
|
|
v000001f7f2c144d0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c14f70_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c14570_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c14890_0 .net "D", 0 0, L_000001f7f2c6a240; 1 drivers
|
|
v000001f7f2c14a70_0 .net "Q", 0 0, v000001f7f2c15510_0; 1 drivers
|
|
v000001f7f2c14610_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f2a0; 1 drivers
|
|
v000001f7f2c14b10_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f2e8; 1 drivers
|
|
v000001f7f2c15510_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c14bb0_0 .net "_w_CLR", 0 0, L_000001f7f2c66bf0; 1 drivers
|
|
v000001f7f2c14d90_0 .net "_w_D", 0 0, L_000001f7f2c66100; 1 drivers
|
|
S_000001f7f2c17a70 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c175c0;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b942e0 .event posedge, v000001f7f2c14bb0_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c17c00 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c175c0;
|
|
.timescale -12 -12;
|
|
S_000001f7f2c172a0 .scope module, "data_reg_reg[7]_i_1" "CARRY4" 3 246, 12 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "CI";
|
|
.port_info 1 /INPUT 1 "CYINIT";
|
|
.port_info 2 /INPUT 4 "DI";
|
|
.port_info 3 /INPUT 4 "S";
|
|
.port_info 4 /OUTPUT 4 "CO";
|
|
.port_info 5 /OUTPUT 4 "O";
|
|
L_000001f7f2c661e0 .functor OR 1, L_000001f7f2c69c00, L_000001f7f2c1eb98, C4<0>, C4<0>;
|
|
L_000001f7f2c6fd70 .functor OR 1, L_000001f7f2c69c00, L_000001f7f2c1eb98, C4<0>, C4<0>;
|
|
L_000001f7f2c6fde0 .functor XOR 4, L_000001f7f2c677c0, L_000001f7f2c69d40, C4<0000>, C4<0000>;
|
|
v000001f7f2c14e30_0 .net "CI", 0 0, L_000001f7f2c69c00; alias, 1 drivers
|
|
v000001f7f2c15010_0 .net "CO", 3 0, L_000001f7f2c6aa60; 1 drivers
|
|
v000001f7f2c150b0_0 .net "CYINIT", 0 0, L_000001f7f2c1eb98; alias, 1 drivers
|
|
v000001f7f2c15150_0 .net "DI", 3 0, L_000001f7f2c6aba0; 1 drivers
|
|
v000001f7f2c198f0_0 .net "O", 3 0, L_000001f7f2c6fde0; 1 drivers
|
|
v000001f7f2c189f0_0 .net "S", 3 0, L_000001f7f2c677c0; 1 drivers
|
|
v000001f7f2c19e90_0 .net *"_ivl_1", 0 0, L_000001f7f2c6a560; 1 drivers
|
|
v000001f7f2c17ff0_0 .net *"_ivl_11", 0 0, L_000001f7f2c6a420; 1 drivers
|
|
v000001f7f2c19cb0_0 .net *"_ivl_15", 0 0, L_000001f7f2c69e80; 1 drivers
|
|
v000001f7f2c19710_0 .net *"_ivl_17", 0 0, L_000001f7f2c6ab00; 1 drivers
|
|
v000001f7f2c19d50_0 .net *"_ivl_2", 0 0, L_000001f7f2c661e0; 1 drivers
|
|
v000001f7f2c19b70_0 .net *"_ivl_21", 0 0, L_000001f7f2c6a6a0; 1 drivers
|
|
v000001f7f2c18810_0 .net *"_ivl_23", 0 0, L_000001f7f2c69b60; 1 drivers
|
|
v000001f7f2c19990_0 .net *"_ivl_28", 0 0, L_000001f7f2c6fd70; 1 drivers
|
|
v000001f7f2c18590_0 .net *"_ivl_30", 3 0, L_000001f7f2c69d40; 1 drivers
|
|
v000001f7f2c18c70_0 .net *"_ivl_5", 0 0, L_000001f7f2c6a1a0; 1 drivers
|
|
v000001f7f2c186d0_0 .net *"_ivl_9", 0 0, L_000001f7f2c6a920; 1 drivers
|
|
v000001f7f2c188b0_0 .net "_w_CO0", 0 0, L_000001f7f2c69de0; 1 drivers
|
|
v000001f7f2c19350_0 .net "_w_CO1", 0 0, L_000001f7f2c6a600; 1 drivers
|
|
v000001f7f2c18a90_0 .net "_w_CO2", 0 0, L_000001f7f2c6aec0; 1 drivers
|
|
v000001f7f2c18950_0 .net "_w_CO3", 0 0, L_000001f7f2c6a7e0; 1 drivers
|
|
L_000001f7f2c6a560 .part L_000001f7f2c677c0, 0, 1;
|
|
L_000001f7f2c6a1a0 .part L_000001f7f2c6aba0, 0, 1;
|
|
L_000001f7f2c69de0 .functor MUXZ 1, L_000001f7f2c6a1a0, L_000001f7f2c661e0, L_000001f7f2c6a560, C4<>;
|
|
L_000001f7f2c6a920 .part L_000001f7f2c677c0, 1, 1;
|
|
L_000001f7f2c6a420 .part L_000001f7f2c6aba0, 1, 1;
|
|
L_000001f7f2c6a600 .functor MUXZ 1, L_000001f7f2c6a420, L_000001f7f2c69de0, L_000001f7f2c6a920, C4<>;
|
|
L_000001f7f2c69e80 .part L_000001f7f2c677c0, 2, 1;
|
|
L_000001f7f2c6ab00 .part L_000001f7f2c6aba0, 2, 1;
|
|
L_000001f7f2c6aec0 .functor MUXZ 1, L_000001f7f2c6ab00, L_000001f7f2c6a600, L_000001f7f2c69e80, C4<>;
|
|
L_000001f7f2c6a6a0 .part L_000001f7f2c677c0, 3, 1;
|
|
L_000001f7f2c69b60 .part L_000001f7f2c6aba0, 3, 1;
|
|
L_000001f7f2c6a7e0 .functor MUXZ 1, L_000001f7f2c69b60, L_000001f7f2c6aec0, L_000001f7f2c6a6a0, C4<>;
|
|
L_000001f7f2c6aa60 .concat [ 1 1 1 1], L_000001f7f2c69de0, L_000001f7f2c6a600, L_000001f7f2c6aec0, L_000001f7f2c6a7e0;
|
|
L_000001f7f2c69d40 .concat [ 1 1 1 1], L_000001f7f2c6fd70, L_000001f7f2c69de0, L_000001f7f2c6a600, L_000001f7f2c6aec0;
|
|
S_000001f7f2c16620 .scope module, "rst_n_IBUF_inst" "IBUF" 3 253, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c6f440 .functor BUFZ 1, v000001f7f2c1c450_0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c18090_0 .net "I", 0 0, v000001f7f2c1c450_0; alias, 1 drivers
|
|
v000001f7f2c18310_0 .net "O", 0 0, L_000001f7f2c6f440; alias, 1 drivers
|
|
S_000001f7f2c16df0 .scope module, "valid_in_IBUF_inst" "IBUF" 3 256, 7 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c6fb40 .functor BUFZ 1, v000001f7f2c1b5f0_0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c19df0_0 .net "I", 0 0, v000001f7f2c1b5f0_0; alias, 1 drivers
|
|
v000001f7f2c19530_0 .net "O", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
S_000001f7f2c16f80 .scope module, "valid_out_OBUF_inst" "OBUF" 3 259, 8 1 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "I";
|
|
.port_info 1 /OUTPUT 1 "O";
|
|
L_000001f7f2c6f520 .functor BUFZ 1, v000001f7f2c183b0_0, C4<0>, C4<0>, C4<0>;
|
|
v000001f7f2c18770_0 .net "I", 0 0, v000001f7f2c183b0_0; alias, 1 drivers
|
|
v000001f7f2c18130_0 .net "O", 0 0, L_000001f7f2c6f520; alias, 1 drivers
|
|
S_000001f7f2c15fe0 .scope module, "valid_out_reg" "FDCE" 3 264, 11 13 0, S_000001f7f2ba6300;
|
|
.timescale -12 -12;
|
|
.port_info 0 /INPUT 1 "C";
|
|
.port_info 1 /INPUT 1 "CE";
|
|
.port_info 2 /INPUT 1 "CLR";
|
|
.port_info 3 /INPUT 1 "D";
|
|
.port_info 4 /OUTPUT 1 "Q";
|
|
P_000001f7f2ba29c0 .param/l "INIT" 0 11 18, C4<0>;
|
|
P_000001f7f2ba29f8 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>;
|
|
P_000001f7f2ba2a30 .param/l "IS_C_INVERTED" 0 11 15, C4<0>;
|
|
P_000001f7f2ba2a68 .param/l "IS_D_INVERTED" 0 11 16, C4<0>;
|
|
L_000001f7f2c1f330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c6ff30 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f330, C4<0>, C4<0>;
|
|
L_000001f7f2c1f378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
|
L_000001f7f2c6f2f0 .functor XOR 1, L_000001f7f2c6fb40, L_000001f7f2c1f378, C4<0>, C4<0>;
|
|
v000001f7f2c18450_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers
|
|
v000001f7f2c181d0_0 .net "CE", 0 0, L_000001f7f2c1ebe0; alias, 1 drivers
|
|
v000001f7f2c18b30_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers
|
|
v000001f7f2c18270_0 .net "D", 0 0, L_000001f7f2c6fb40; alias, 1 drivers
|
|
v000001f7f2c195d0_0 .net "Q", 0 0, v000001f7f2c183b0_0; alias, 1 drivers
|
|
v000001f7f2c19670_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f330; 1 drivers
|
|
v000001f7f2c18bd0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f378; 1 drivers
|
|
v000001f7f2c183b0_0 .var "_r_Q", 0 0;
|
|
v000001f7f2c184f0_0 .net "_w_CLR", 0 0, L_000001f7f2c6ff30; 1 drivers
|
|
v000001f7f2c197b0_0 .net "_w_D", 0 0, L_000001f7f2c6f2f0; 1 drivers
|
|
S_000001f7f2c167b0 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c15fe0;
|
|
.timescale -12 -12;
|
|
E_000001f7f2b93f60 .event posedge, v000001f7f2c184f0_0, v000001f7f2b9a180_0;
|
|
S_000001f7f2c16170 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c15fe0;
|
|
.timescale -12 -12;
|
|
.scope S_000001f7f2c10140;
|
|
T_0 ;
|
|
%wait E_000001f7f2b92de0;
|
|
%load/vec4 v000001f7f2c12100_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_0.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c13320_0, 0;
|
|
%jmp T_0.1;
|
|
T_0.0 ;
|
|
%load/vec4 v000001f7f2c0b430_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_0.2, 8;
|
|
%load/vec4 v000001f7f2c13280_0;
|
|
%assign/vec4 v000001f7f2c13320_0, 0;
|
|
T_0.2 ;
|
|
T_0.1 ;
|
|
%jmp T_0;
|
|
.thread T_0;
|
|
.scope S_000001f7f2c11590;
|
|
T_1 ;
|
|
%fork t_1, S_000001f7f2c10780;
|
|
%jmp t_0;
|
|
.scope S_000001f7f2c10780;
|
|
t_1 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c13320_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c11590;
|
|
t_0 %join;
|
|
%end;
|
|
.thread T_1;
|
|
.scope S_000001f7f2c10c30;
|
|
T_2 ;
|
|
%wait E_000001f7f2b92ee0;
|
|
%load/vec4 v000001f7f2c13dc0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_2.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c13b40_0, 0;
|
|
%jmp T_2.1;
|
|
T_2.0 ;
|
|
%load/vec4 v000001f7f2c12240_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_2.2, 8;
|
|
%load/vec4 v000001f7f2c13000_0;
|
|
%assign/vec4 v000001f7f2c13b40_0, 0;
|
|
T_2.2 ;
|
|
T_2.1 ;
|
|
%jmp T_2;
|
|
.thread T_2;
|
|
.scope S_000001f7f2c11270;
|
|
T_3 ;
|
|
%fork t_3, S_000001f7f2c11720;
|
|
%jmp t_2;
|
|
.scope S_000001f7f2c11720;
|
|
t_3 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c13b40_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c11270;
|
|
t_2 %join;
|
|
%end;
|
|
.thread T_3;
|
|
.scope S_000001f7f2c102d0;
|
|
T_4 ;
|
|
%wait E_000001f7f2b930e0;
|
|
%load/vec4 v000001f7f2c13960_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c12ba0_0, 0;
|
|
%jmp T_4.1;
|
|
T_4.0 ;
|
|
%load/vec4 v000001f7f2c12d80_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.2, 8;
|
|
%load/vec4 v000001f7f2c13a00_0;
|
|
%assign/vec4 v000001f7f2c12ba0_0, 0;
|
|
T_4.2 ;
|
|
T_4.1 ;
|
|
%jmp T_4;
|
|
.thread T_4;
|
|
.scope S_000001f7f2c10f50;
|
|
T_5 ;
|
|
%fork t_5, S_000001f7f2c10aa0;
|
|
%jmp t_4;
|
|
.scope S_000001f7f2c10aa0;
|
|
t_5 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c12ba0_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c10f50;
|
|
t_4 %join;
|
|
%end;
|
|
.thread T_5;
|
|
.scope S_000001f7f2c11a40;
|
|
T_6 ;
|
|
%wait E_000001f7f2b94020;
|
|
%load/vec4 v000001f7f2c12c40_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_6.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c129c0_0, 0;
|
|
%jmp T_6.1;
|
|
T_6.0 ;
|
|
%load/vec4 v000001f7f2c12060_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_6.2, 8;
|
|
%load/vec4 v000001f7f2c124c0_0;
|
|
%assign/vec4 v000001f7f2c129c0_0, 0;
|
|
T_6.2 ;
|
|
T_6.1 ;
|
|
%jmp T_6;
|
|
.thread T_6;
|
|
.scope S_000001f7f2c10910;
|
|
T_7 ;
|
|
%fork t_7, S_000001f7f2c10dc0;
|
|
%jmp t_6;
|
|
.scope S_000001f7f2c10dc0;
|
|
t_7 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c129c0_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c10910;
|
|
t_6 %join;
|
|
%end;
|
|
.thread T_7;
|
|
.scope S_000001f7f2c16ad0;
|
|
T_8 ;
|
|
%wait E_000001f7f2b93ea0;
|
|
%load/vec4 v000001f7f2c15830_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_8.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c15b50_0, 0;
|
|
%jmp T_8.1;
|
|
T_8.0 ;
|
|
%load/vec4 v000001f7f2c156f0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_8.2, 8;
|
|
%load/vec4 v000001f7f2c13fd0_0;
|
|
%assign/vec4 v000001f7f2c15b50_0, 0;
|
|
T_8.2 ;
|
|
T_8.1 ;
|
|
%jmp T_8;
|
|
.thread T_8;
|
|
.scope S_000001f7f2c11d60;
|
|
T_9 ;
|
|
%fork t_9, S_000001f7f2c16940;
|
|
%jmp t_8;
|
|
.scope S_000001f7f2c16940;
|
|
t_9 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c15b50_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c11d60;
|
|
t_8 %join;
|
|
%end;
|
|
.thread T_9;
|
|
.scope S_000001f7f2c16490;
|
|
T_10 ;
|
|
%wait E_000001f7f2b943e0;
|
|
%load/vec4 v000001f7f2c142f0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_10.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c14250_0, 0;
|
|
%jmp T_10.1;
|
|
T_10.0 ;
|
|
%load/vec4 v000001f7f2c15ab0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_10.2, 8;
|
|
%load/vec4 v000001f7f2c155b0_0;
|
|
%assign/vec4 v000001f7f2c14250_0, 0;
|
|
T_10.2 ;
|
|
T_10.1 ;
|
|
%jmp T_10;
|
|
.thread T_10;
|
|
.scope S_000001f7f2c16c60;
|
|
T_11 ;
|
|
%fork t_11, S_000001f7f2c16300;
|
|
%jmp t_10;
|
|
.scope S_000001f7f2c16300;
|
|
t_11 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c14250_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c16c60;
|
|
t_10 %join;
|
|
%end;
|
|
.thread T_11;
|
|
.scope S_000001f7f2c17d90;
|
|
T_12 ;
|
|
%wait E_000001f7f2b93da0;
|
|
%load/vec4 v000001f7f2c15470_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_12.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c14430_0, 0;
|
|
%jmp T_12.1;
|
|
T_12.0 ;
|
|
%load/vec4 v000001f7f2c158d0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_12.2, 8;
|
|
%load/vec4 v000001f7f2c147f0_0;
|
|
%assign/vec4 v000001f7f2c14430_0, 0;
|
|
T_12.2 ;
|
|
T_12.1 ;
|
|
%jmp T_12;
|
|
.thread T_12;
|
|
.scope S_000001f7f2c17430;
|
|
T_13 ;
|
|
%fork t_13, S_000001f7f2c178e0;
|
|
%jmp t_12;
|
|
.scope S_000001f7f2c178e0;
|
|
t_13 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c14430_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c17430;
|
|
t_12 %join;
|
|
%end;
|
|
.thread T_13;
|
|
.scope S_000001f7f2c17a70;
|
|
T_14 ;
|
|
%wait E_000001f7f2b942e0;
|
|
%load/vec4 v000001f7f2c14bb0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c15510_0, 0;
|
|
%jmp T_14.1;
|
|
T_14.0 ;
|
|
%load/vec4 v000001f7f2c14f70_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_14.2, 8;
|
|
%load/vec4 v000001f7f2c14d90_0;
|
|
%assign/vec4 v000001f7f2c15510_0, 0;
|
|
T_14.2 ;
|
|
T_14.1 ;
|
|
%jmp T_14;
|
|
.thread T_14;
|
|
.scope S_000001f7f2c175c0;
|
|
T_15 ;
|
|
%fork t_15, S_000001f7f2c17c00;
|
|
%jmp t_14;
|
|
.scope S_000001f7f2c17c00;
|
|
t_15 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c15510_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c175c0;
|
|
t_14 %join;
|
|
%end;
|
|
.thread T_15;
|
|
.scope S_000001f7f2c167b0;
|
|
T_16 ;
|
|
%wait E_000001f7f2b93f60;
|
|
%load/vec4 v000001f7f2c184f0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c183b0_0, 0;
|
|
%jmp T_16.1;
|
|
T_16.0 ;
|
|
%load/vec4 v000001f7f2c181d0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_16.2, 8;
|
|
%load/vec4 v000001f7f2c197b0_0;
|
|
%assign/vec4 v000001f7f2c183b0_0, 0;
|
|
T_16.2 ;
|
|
T_16.1 ;
|
|
%jmp T_16;
|
|
.thread T_16;
|
|
.scope S_000001f7f2c15fe0;
|
|
T_17 ;
|
|
%fork t_17, S_000001f7f2c16170;
|
|
%jmp t_16;
|
|
.scope S_000001f7f2c16170;
|
|
t_17 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c183b0_0, 0, 1;
|
|
%end;
|
|
.scope S_000001f7f2c15fe0;
|
|
t_16 %join;
|
|
%end;
|
|
.thread T_17;
|
|
.scope S_000001f7f2b9eb50;
|
|
T_18 ;
|
|
%vpi_call 2 37 "$dumpfile", "EzLogic_tb.vcd" {0 0 0};
|
|
%vpi_call 2 38 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001f7f2b9eb50 {0 0 0};
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c1aa10_0, 0, 1;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c1c450_0, 0, 1;
|
|
%pushi/vec4 0, 0, 8;
|
|
%store/vec4 v000001f7f2c1c630_0, 0, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c1b5f0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 7;
|
|
%store/vec4 v000001f7f2c1a1f0_0, 0, 7;
|
|
%pushi/vec4 0, 0, 7;
|
|
%store/vec4 v000001f7f2c1bc30_0, 0, 7;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v000001f7f2c1b7d0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 336;
|
|
%store/vec4 v000001f7f2c1ac90_0, 0, 336;
|
|
%delay 4000000, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v000001f7f2c1c450_0, 0, 1;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v000001f7f2c1b7d0_0, 0, 1;
|
|
%wait E_000001f7f2b95560;
|
|
%delay 4000000, 0;
|
|
%load/vec4 v000001f7f2c1ae70_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_18.0, 8;
|
|
%vpi_call 2 53 "$display", "Great! You've found the correct flag!" {0 0 0};
|
|
%jmp T_18.1;
|
|
T_18.0 ;
|
|
%vpi_call 2 56 "$display", "Binary Data: %b", v000001f7f2c1ac90_0 {0 0 0};
|
|
%vpi_call 2 57 "$display", "Binary Data: %b", v000001f7f2c1b550_0 {0 0 0};
|
|
%vpi_call 2 58 "$display", "Hexadecimal Data: %h", v000001f7f2c1ac90_0 {0 0 0};
|
|
%vpi_call 2 59 "$display", "Haha, try again!" {0 0 0};
|
|
T_18.1 ;
|
|
%delay 20000000, 0;
|
|
%vpi_call 2 62 "$finish" {0 0 0};
|
|
%end;
|
|
.thread T_18;
|
|
.scope S_000001f7f2b9eb50;
|
|
T_19 ;
|
|
%wait E_000001f7f2b95b20;
|
|
%load/vec4 v000001f7f2c1b7d0_0;
|
|
%pad/u 32;
|
|
%cmpi/e 1, 0, 32;
|
|
%jmp/0xz T_19.0, 4;
|
|
%load/vec4 v000001f7f2c1a1f0_0;
|
|
%pad/u 32;
|
|
%cmpi/u 42, 0, 32;
|
|
%jmp/0xz T_19.2, 5;
|
|
%load/vec4 v000001f7f2c1a1f0_0;
|
|
%addi 1, 0, 7;
|
|
%assign/vec4 v000001f7f2c1a1f0_0, 0;
|
|
%ix/getv 4, v000001f7f2c1a1f0_0;
|
|
%load/vec4a v000001f7f2c1be10, 4;
|
|
%assign/vec4 v000001f7f2c1c630_0, 0;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v000001f7f2c1b5f0_0, 0;
|
|
%jmp T_19.3;
|
|
T_19.2 ;
|
|
%pushi/vec4 0, 0, 8;
|
|
%assign/vec4 v000001f7f2c1c630_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c1b5f0_0, 0;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v000001f7f2c1b7d0_0, 0;
|
|
T_19.3 ;
|
|
T_19.0 ;
|
|
%jmp T_19;
|
|
.thread T_19;
|
|
.scope S_000001f7f2b9eb50;
|
|
T_20 ;
|
|
%wait E_000001f7f2b95b20;
|
|
%load/vec4 v000001f7f2c1b190_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_20.0, 8;
|
|
%load/vec4 v000001f7f2c1bc30_0;
|
|
%addi 1, 0, 7;
|
|
%assign/vec4 v000001f7f2c1bc30_0, 0;
|
|
%load/vec4 v000001f7f2c1add0_0;
|
|
%ix/load 5, 0, 0;
|
|
%pushi/vec4 328, 0, 34;
|
|
%load/vec4 v000001f7f2c1bc30_0;
|
|
%pad/u 32;
|
|
%muli 8, 0, 32;
|
|
%pad/u 34;
|
|
%sub;
|
|
%ix/vec4/s 4;
|
|
%assign/vec4/off/d v000001f7f2c1ac90_0, 4, 5;
|
|
T_20.0 ;
|
|
%jmp T_20;
|
|
.thread T_20;
|
|
.scope S_000001f7f2b9eb50;
|
|
T_21 ;
|
|
%delay 1000000, 0;
|
|
%load/vec4 v000001f7f2c1aa10_0;
|
|
%inv;
|
|
%store/vec4 v000001f7f2c1aa10_0, 0, 1;
|
|
%jmp T_21;
|
|
.thread T_21;
|
|
# The file index is used to find the file name in the following table.
|
|
:file_names 13;
|
|
"N/A";
|
|
"<interactive>";
|
|
"./problem/EzLogic_tb.v";
|
|
"./problem/EzLogic_top_synth.v";
|
|
"./behavioral models/GND.v";
|
|
"./behavioral models/VCC.v";
|
|
"./behavioral models/BUFG.v";
|
|
"./behavioral models/IBUF.v";
|
|
"./behavioral models/OBUF.v";
|
|
"./behavioral models/LUT2.v";
|
|
"./behavioral models/LUT1.v";
|
|
"./behavioral models/FDCE.v";
|
|
"./behavioral models/CARRY4.v";
|