92 lines
2.2 KiB
Verilog
92 lines
2.2 KiB
Verilog
`timescale 1us / 100ns
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module EzLogic_tb #(
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parameter FLAG_TO_TEST = "0o",
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parameter N = 42
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)();
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reg clk;
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reg rst_n;
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reg valid_in;
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reg start;
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reg [7:0] data_in;
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reg [6:0] counter;
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reg [6:0] counter2;
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wire [7:0] data_out;
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wire valid_out;
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reg [0:8*N-1] data_out_all;
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wire success;
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wire [7:0] flag_test_arr [0:N-1];
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genvar i;
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generate
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for (i=0;i<N;i=i+1) begin
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assign flag_test_arr[N-1-i] = FLAG_TO_TEST[(i*8)+:8];
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end
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endgenerate
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EzLogic_top inst(
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.clk(clk),
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.rst_n(rst_n),
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.data_in(data_in),
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.valid_in(valid_in),
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.data_out(data_out),
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.valid_out(valid_out)
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);
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initial begin
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$dumpfile("EzLogic_tb.vcd");
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$dumpvars(0, EzLogic_tb);
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clk = 0;
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rst_n = 0;
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data_in = 0;
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valid_in = 0;
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counter = 0;
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counter2 = 0;
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start = 0;
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data_out_all = 0;
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#4
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rst_n = 1;
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start = 1;
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@(negedge start);
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#4
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if (success) begin
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$display("Great! You've found the correct flag!");
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end
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else begin
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$display("Binary Data: %b", data_out_all);
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$display("Binary Data: %b", data_std);
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$display("Hexadecimal Data: %h", data_out_all);
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$display("Haha, try again!");
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end
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#20
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$finish();
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end
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always @(posedge clk) begin
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if (start == 1) begin
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if (counter < N) begin
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counter <= counter + 1;
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data_in <= flag_test_arr[counter];
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valid_in <= 1;
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end
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else begin
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data_in <= 0;
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valid_in <= 0;
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start <= 0;
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end
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end
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end
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always @(posedge clk) begin
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if (valid_out) begin
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counter2 <= counter2 + 1;
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data_out_all[(counter2)*8 +: 8] <= data_out;
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end
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end
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wire [0:8*N-1] data_std = 'h30789d5692f2fe23bb2c5d9e16406653b6cb217c952998ce17b7143788d949952680b4bce4c30a96c753;
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assign success = (data_std == data_out_all);
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always #1 clk = ~clk;
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endmodule
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