18 lines
249 B
Verilog
18 lines
249 B
Verilog
`ifdef verilator3
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`else
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`timescale 1 ps / 1 ps
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`endif
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/* verilator coverage_off */
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module MUXF7
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(
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input wire I0, I1, S,
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output wire O
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);
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wire [1:0] w_data = { I1, I0 };
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assign O = w_data[S];
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endmodule
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/* verilator coverage_on */
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