27 lines
466 B
Verilog
27 lines
466 B
Verilog
`ifdef verilator3
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`else
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`timescale 1 ps / 1 ps
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`endif
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//
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// LUT4 primitive for Xilinx FPGAs
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// Compatible with Verilator tool (www.veripool.org)
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// Copyright (c) 2019-2022 Frédéric REQUIN
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// License : BSD
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//
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/* verilator coverage_off */
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module LUT4
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#(
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parameter [15:0] INIT = 16'h0000
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)
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(
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input wire I0, I1, I2, I3,
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output wire O
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);
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wire [3:0] _w_idx = { I3, I2, I1, I0 };
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assign O = INIT[_w_idx];
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endmodule
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/* verilator coverage_on */
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