CTF/0ctf/EzLogic/EzLogic_tb.vcd

$date
	Sun Dec 22 12:30:21 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module EzLogic_tb $end
$var wire 336 ! data_std [0:335] $end
$var wire 1 " valid_out $end
$var wire 1 # success $end
$var wire 8 $ data_out [7:0] $end
$var parameter 16 % FLAG_TO_TEST $end
$var parameter 32 & N $end
$var reg 1 ' clk $end
$var reg 7 ( counter [6:0] $end
$var reg 7 ) counter2 [6:0] $end
$var reg 8 * data_in [7:0] $end
$var reg 336 + data_out_all [0:335] $end
$var reg 1 , rst_n $end
$var reg 1 - start $end
$var reg 1 . valid_in $end
$scope begin genblk1[0] $end
$var parameter 2 / i $end
$upscope $end
$scope begin genblk1[1] $end
$var parameter 2 0 i $end
$upscope $end
$scope begin genblk1[2] $end
$var parameter 3 1 i $end
$upscope $end
$scope begin genblk1[3] $end
$var parameter 3 2 i $end
$upscope $end
$scope begin genblk1[4] $end
$var parameter 4 3 i $end
$upscope $end
$scope begin genblk1[5] $end
$var parameter 4 4 i $end
$upscope $end
$scope begin genblk1[6] $end
$var parameter 4 5 i $end
$upscope $end
$scope begin genblk1[7] $end
$var parameter 4 6 i $end
$upscope $end
$scope begin genblk1[8] $end
$var parameter 5 7 i $end
$upscope $end
$scope begin genblk1[9] $end
$var parameter 5 8 i $end
$upscope $end
$scope begin genblk1[10] $end
$var parameter 5 9 i $end
$upscope $end
$scope begin genblk1[11] $end
$var parameter 5 : i $end
$upscope $end
$scope begin genblk1[12] $end
$var parameter 5 ; i $end
$upscope $end
$scope begin genblk1[13] $end
$var parameter 5 < i $end
$upscope $end
$scope begin genblk1[14] $end
$var parameter 5 = i $end
$upscope $end
$scope begin genblk1[15] $end
$var parameter 5 > i $end
$upscope $end
$scope begin genblk1[16] $end
$var parameter 6 ? i $end
$upscope $end
$scope begin genblk1[17] $end
$var parameter 6 @ i $end
$upscope $end
$scope begin genblk1[18] $end
$var parameter 6 A i $end
$upscope $end
$scope begin genblk1[19] $end
$var parameter 6 B i $end
$upscope $end
$scope begin genblk1[20] $end
$var parameter 6 C i $end
$upscope $end
$scope begin genblk1[21] $end
$var parameter 6 D i $end
$upscope $end
$scope begin genblk1[22] $end
$var parameter 6 E i $end
$upscope $end
$scope begin genblk1[23] $end
$var parameter 6 F i $end
$upscope $end
$scope begin genblk1[24] $end
$var parameter 6 G i $end
$upscope $end
$scope begin genblk1[25] $end
$var parameter 6 H i $end
$upscope $end
$scope begin genblk1[26] $end
$var parameter 6 I i $end
$upscope $end
$scope begin genblk1[27] $end
$var parameter 6 J i $end
$upscope $end
$scope begin genblk1[28] $end
$var parameter 6 K i $end
$upscope $end
$scope begin genblk1[29] $end
$var parameter 6 L i $end
$upscope $end
$scope begin genblk1[30] $end
$var parameter 6 M i $end
$upscope $end
$scope begin genblk1[31] $end
$var parameter 6 N i $end
$upscope $end
$scope begin genblk1[32] $end
$var parameter 7 O i $end
$upscope $end
$scope begin genblk1[33] $end
$var parameter 7 P i $end
$upscope $end
$scope begin genblk1[34] $end
$var parameter 7 Q i $end
$upscope $end
$scope begin genblk1[35] $end
$var parameter 7 R i $end
$upscope $end
$scope begin genblk1[36] $end
$var parameter 7 S i $end
$upscope $end
$scope begin genblk1[37] $end
$var parameter 7 T i $end
$upscope $end
$scope begin genblk1[38] $end
$var parameter 7 U i $end
$upscope $end
$scope begin genblk1[39] $end
$var parameter 7 V i $end
$upscope $end
$scope begin genblk1[40] $end
$var parameter 7 W i $end
$upscope $end
$scope begin genblk1[41] $end
$var parameter 7 X i $end
$upscope $end
$scope module inst $end
$var wire 1 Y \<const0> $end
$var wire 1 Z \<const1> $end
$var wire 1 ' clk $end
$var wire 8 [ data_in [7:0] $end
$var wire 1 , rst_n $end
$var wire 1 . valid_in $end
$var wire 1 \ valid_out_OBUF $end
$var wire 1 " valid_out $end
$var wire 1 ] valid_in_IBUF $end
$var wire 1 ^ rst_n_IBUF $end
$var wire 8 _ p_0_in [7:0] $end
$var wire 1 ` \data_reg_reg[7]_i_1_n_3 $end
$var wire 1 a \data_reg_reg[7]_i_1_n_2 $end
$var wire 1 b \data_reg_reg[7]_i_1_n_1 $end
$var wire 1 c \data_reg_reg[3]_i_1_n_3 $end
$var wire 1 d \data_reg_reg[3]_i_1_n_2 $end
$var wire 1 e \data_reg_reg[3]_i_1_n_1 $end
$var wire 1 f \data_reg_reg[3]_i_1_n_0 $end
$var wire 1 g \data_reg[7]_i_6_n_0 $end
$var wire 1 h \data_reg[7]_i_5_n_0 $end
$var wire 1 i \data_reg[7]_i_4_n_0 $end
$var wire 1 j \data_reg[7]_i_3_n_0 $end
$var wire 1 k \data_reg[7]_i_2_n_0 $end
$var wire 1 l \data_reg[3]_i_5_n_0 $end
$var wire 1 m \data_reg[3]_i_4_n_0 $end
$var wire 1 n \data_reg[3]_i_3_n_0 $end
$var wire 1 o \data_reg[3]_i_2_n_0 $end
$var wire 8 p data_out_OBUF [7:0] $end
$var wire 8 q data_out [7:0] $end
$var wire 8 r data_in_IBUF [7:0] $end
$var wire 1 s clk_IBUF_BUFG $end
$var wire 1 t clk_IBUF $end
$scope module GND $end
$var wire 1 Y G $end
$upscope $end
$scope module VCC $end
$var wire 1 Z P $end
$upscope $end
$scope module clk_IBUF_BUFG_inst $end
$var wire 1 s O $end
$var wire 1 t I $end
$upscope $end
$scope module clk_IBUF_inst $end
$var wire 1 ' I $end
$var wire 1 t O $end
$upscope $end
$scope module data_in_IBUF[0]_inst $end
$var wire 1 u I $end
$var wire 1 v O $end
$upscope $end
$scope module data_in_IBUF[1]_inst $end
$var wire 1 w I $end
$var wire 1 x O $end
$upscope $end
$scope module data_in_IBUF[2]_inst $end
$var wire 1 y I $end
$var wire 1 z O $end
$upscope $end
$scope module data_in_IBUF[3]_inst $end
$var wire 1 { I $end
$var wire 1 | O $end
$upscope $end
$scope module data_in_IBUF[4]_inst $end
$var wire 1 } I $end
$var wire 1 ~ O $end
$upscope $end
$scope module data_in_IBUF[5]_inst $end
$var wire 1 !" I $end
$var wire 1 "" O $end
$upscope $end
$scope module data_in_IBUF[6]_inst $end
$var wire 1 #" I $end
$var wire 1 $" O $end
$upscope $end
$scope module data_in_IBUF[7]_inst $end
$var wire 1 %" I $end
$var wire 1 &" O $end
$upscope $end
$scope module data_out_OBUF[0]_inst $end
$var wire 1 '" I $end
$var wire 1 (" O $end
$upscope $end
$scope module data_out_OBUF[1]_inst $end
$var wire 1 )" I $end
$var wire 1 *" O $end
$upscope $end
$scope module data_out_OBUF[2]_inst $end
$var wire 1 +" I $end
$var wire 1 ," O $end
$upscope $end
$scope module data_out_OBUF[3]_inst $end
$var wire 1 -" I $end
$var wire 1 ." O $end
$upscope $end
$scope module data_out_OBUF[4]_inst $end
$var wire 1 /" I $end
$var wire 1 0" O $end
$upscope $end
$scope module data_out_OBUF[5]_inst $end
$var wire 1 1" I $end
$var wire 1 2" O $end
$upscope $end
$scope module data_out_OBUF[6]_inst $end
$var wire 1 3" I $end
$var wire 1 4" O $end
$upscope $end
$scope module data_out_OBUF[7]_inst $end
$var wire 1 5" I $end
$var wire 1 6" O $end
$upscope $end
$scope module data_reg[3]_i_2 $end
$var wire 1 7" I0 $end
$var wire 1 8" I1 $end
$var wire 2 9" _w_idx [1:0] $end
$var wire 1 o O $end
$var parameter 4 :" INIT $end
$upscope $end
$scope module data_reg[3]_i_3 $end
$var wire 1 ;" I0 $end
$var wire 1 <" I1 $end
$var wire 2 =" _w_idx [1:0] $end
$var wire 1 n O $end
$var parameter 4 >" INIT $end
$upscope $end
$scope module data_reg[3]_i_4 $end
$var wire 1 ?" I0 $end
$var wire 1 @" I1 $end
$var wire 2 A" _w_idx [1:0] $end
$var wire 1 m O $end
$var parameter 4 B" INIT $end
$upscope $end
$scope module data_reg[3]_i_5 $end
$var wire 1 C" I0 $end
$var wire 1 D" I1 $end
$var wire 2 E" _w_idx [1:0] $end
$var wire 1 l O $end
$var parameter 4 F" INIT $end
$upscope $end
$scope module data_reg[7]_i_2 $end
$var wire 1 k O $end
$var wire 1 ^ I0 $end
$var parameter 2 G" INIT $end
$upscope $end
$scope module data_reg[7]_i_3 $end
$var wire 1 H" I0 $end
$var wire 1 I" I1 $end
$var wire 2 J" _w_idx [1:0] $end
$var wire 1 j O $end
$var parameter 4 K" INIT $end
$upscope $end
$scope module data_reg[7]_i_4 $end
$var wire 1 L" I0 $end
$var wire 1 M" I1 $end
$var wire 2 N" _w_idx [1:0] $end
$var wire 1 i O $end
$var parameter 4 O" INIT $end
$upscope $end
$scope module data_reg[7]_i_5 $end
$var wire 1 P" I0 $end
$var wire 1 Q" I1 $end
$var wire 2 R" _w_idx [1:0] $end
$var wire 1 h O $end
$var parameter 4 S" INIT $end
$upscope $end
$scope module data_reg[7]_i_6 $end
$var wire 1 T" I0 $end
$var wire 1 U" I1 $end
$var wire 2 V" _w_idx [1:0] $end
$var wire 1 g O $end
$var parameter 4 W" INIT $end
$upscope $end
$scope module data_reg_reg[0] $end
$var wire 1 s C $end
$var wire 1 k CLR $end
$var wire 1 X" D $end
$var wire 1 Y" _w_CLR $end
$var wire 1 Z" _w_D $end
$var wire 1 [" Q $end
$var wire 1 ] CE $end
$var parameter 1 \" INIT $end
$var parameter 1 ]" IS_CLR_INVERTED $end
$var parameter 1 ^" IS_C_INVERTED $end
$var parameter 1 _" IS_D_INVERTED $end
$var reg 1 [" _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$scope module data_reg_reg[1] $end
$var wire 1 s C $end
$var wire 1 k CLR $end
$var wire 1 `" D $end
$var wire 1 a" _w_CLR $end
$var wire 1 b" _w_D $end
$var wire 1 c" Q $end
$var wire 1 ] CE $end
$var parameter 1 d" INIT $end
$var parameter 1 e" IS_CLR_INVERTED $end
$var parameter 1 f" IS_C_INVERTED $end
$var parameter 1 g" IS_D_INVERTED $end
$var reg 1 c" _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$scope module data_reg_reg[2] $end
$var wire 1 s C $end
$var wire 1 k CLR $end
$var wire 1 h" D $end
$var wire 1 i" _w_CLR $end
$var wire 1 j" _w_D $end
$var wire 1 k" Q $end
$var wire 1 ] CE $end
$var parameter 1 l" INIT $end
$var parameter 1 m" IS_CLR_INVERTED $end
$var parameter 1 n" IS_C_INVERTED $end
$var parameter 1 o" IS_D_INVERTED $end
$var reg 1 k" _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$scope module data_reg_reg[3] $end
$var wire 1 s C $end
$var wire 1 k CLR $end
$var wire 1 p" D $end
$var wire 1 q" _w_CLR $end
$var wire 1 r" _w_D $end
$var wire 1 s" Q $end
$var wire 1 ] CE $end
$var parameter 1 t" INIT $end
$var parameter 1 u" IS_CLR_INVERTED $end
$var parameter 1 v" IS_C_INVERTED $end
$var parameter 1 w" IS_D_INVERTED $end
$var reg 1 s" _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$scope module data_reg_reg[3]_i_1 $end
$var wire 1 Y CI $end
$var wire 1 Y CYINIT $end
$var wire 4 x" DI [3:0] $end
$var wire 4 y" O [3:0] $end
$var wire 4 z" S [3:0] $end
$var wire 1 {" _w_CO3 $end
$var wire 1 |" _w_CO2 $end
$var wire 1 }" _w_CO1 $end
$var wire 1 ~" _w_CO0 $end
$var wire 4 !# CO [3:0] $end
$upscope $end
$scope module data_reg_reg[4] $end
$var wire 1 s C $end
$var wire 1 k CLR $end
$var wire 1 "# D $end
$var wire 1 ## _w_CLR $end
$var wire 1 $# _w_D $end
$var wire 1 %# Q $end
$var wire 1 ] CE $end
$var parameter 1 &# INIT $end
$var parameter 1 '# IS_CLR_INVERTED $end
$var parameter 1 (# IS_C_INVERTED $end
$var parameter 1 )# IS_D_INVERTED $end
$var reg 1 %# _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$scope module data_reg_reg[5] $end
$var wire 1 s C $end
$var wire 1 k CLR $end
$var wire 1 *# D $end
$var wire 1 +# _w_CLR $end
$var wire 1 ,# _w_D $end
$var wire 1 -# Q $end
$var wire 1 ] CE $end
$var parameter 1 .# INIT $end
$var parameter 1 /# IS_CLR_INVERTED $end
$var parameter 1 0# IS_C_INVERTED $end
$var parameter 1 1# IS_D_INVERTED $end
$var reg 1 -# _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$scope module data_reg_reg[6] $end
$var wire 1 s C $end
$var wire 1 k CLR $end
$var wire 1 2# D $end
$var wire 1 3# _w_CLR $end
$var wire 1 4# _w_D $end
$var wire 1 5# Q $end
$var wire 1 ] CE $end
$var parameter 1 6# INIT $end
$var parameter 1 7# IS_CLR_INVERTED $end
$var parameter 1 8# IS_C_INVERTED $end
$var parameter 1 9# IS_D_INVERTED $end
$var reg 1 5# _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$scope module data_reg_reg[7] $end
$var wire 1 s C $end
$var wire 1 k CLR $end
$var wire 1 :# D $end
$var wire 1 ;# _w_CLR $end
$var wire 1 <# _w_D $end
$var wire 1 =# Q $end
$var wire 1 ] CE $end
$var parameter 1 ># INIT $end
$var parameter 1 ?# IS_CLR_INVERTED $end
$var parameter 1 @# IS_C_INVERTED $end
$var parameter 1 A# IS_D_INVERTED $end
$var reg 1 =# _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$scope module data_reg_reg[7]_i_1 $end
$var wire 1 f CI $end
$var wire 1 Y CYINIT $end
$var wire 4 B# DI [3:0] $end
$var wire 4 C# O [3:0] $end
$var wire 4 D# S [3:0] $end
$var wire 1 E# _w_CO3 $end
$var wire 1 F# _w_CO2 $end
$var wire 1 G# _w_CO1 $end
$var wire 1 H# _w_CO0 $end
$var wire 4 I# CO [3:0] $end
$upscope $end
$scope module rst_n_IBUF_inst $end
$var wire 1 , I $end
$var wire 1 ^ O $end
$upscope $end
$scope module valid_in_IBUF_inst $end
$var wire 1 . I $end
$var wire 1 ] O $end
$upscope $end
$scope module valid_out_OBUF_inst $end
$var wire 1 " O $end
$var wire 1 \ I $end
$upscope $end
$scope module valid_out_reg $end
$var wire 1 s C $end
$var wire 1 Z CE $end
$var wire 1 k CLR $end
$var wire 1 ] D $end
$var wire 1 J# _w_CLR $end
$var wire 1 K# _w_D $end
$var wire 1 \ Q $end
$var parameter 1 L# INIT $end
$var parameter 1 M# IS_CLR_INVERTED $end
$var parameter 1 N# IS_C_INVERTED $end
$var parameter 1 O# IS_D_INVERTED $end
$var reg 1 \ _r_Q $end
$scope begin GEN_CLK_POS $end
$upscope $end
$scope begin INIT_STATE $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
0O#
0N#
0M#
0L#
0A#
0@#
0?#
0>#
09#
08#
07#
06#
01#
00#
0/#
0.#
0)#
0(#
0'#
0&#
0w"
0v"
0u"
0t"
0o"
0n"
0m"
0l"
0g"
0f"
0e"
0d"
0_"
0^"
0]"
0\"
b110 W"
b110 S"
b110 O"
b110 K"
b1 G"
b110 F"
b110 B"
b110 >"
b110 :"
b101001 X
b101000 W
b100111 V
b100110 U
b100101 T
b100100 S
b100011 R
b100010 Q
b100001 P
b100000 O
b11111 N
b11110 M
b11101 L
b11100 K
b11011 J
b11010 I
b11001 H
b11000 G
b10111 F
b10110 E
b10101 D
b10100 C
b10011 B
b10010 A
b10001 @
b10000 ?
b1111 >
b1110 =
b1101 <
b1100 ;
b1011 :
b1010 9
b1001 8
b1000 7
b111 6
b110 5
b101 4
b100 3
b11 2
b10 1
b1 0
b0 /
b101010 &
b11000001101111 %
$end
#0
$dumpvars
0K#
1J#
b0 I#
0H#
0G#
0F#
0E#
b0 D#
b0 C#
b0 B#
0=#
0<#
1;#
0:#
05#
04#
13#
02#
0-#
0,#
1+#
0*#
0%#
0$#
1##
0"#
b0 !#
0~"
0}"
0|"
0{"
b0 z"
b0 y"
b0 x"
0s"
0r"
1q"
0p"
0k"
0j"
1i"
0h"
0c"
0b"
1a"
0`"
0["
0Z"
1Y"
0X"
b0 V"
0U"
0T"
b0 R"
0Q"
0P"
b0 N"
0M"
0L"
b0 J"
0I"
0H"
b0 E"
0D"
0C"
b0 A"
0@"
0?"
b0 ="
0<"
0;"
b0 9"
08"
07"
06"
05"
04"
03"
02"
01"
00"
0/"
0."
0-"
0,"
0+"
0*"
0)"
0("
0'"
0&"
0%"
0$"
0#"
0""
0!"
0~
0}
0|
0{
0z
0y
0x
0w
0v
0u
0t
0s
b0 r
b0 q
b0 p
0o
0n
0m
0l
1k
0j
0i
0h
0g
0f
0e
0d
0c
0b
0a
0`
b0 _
0^
0]
0\
b0 [
1Z
0Y
0.
0-
0,
b0 +
b0 *
b0 )
b0 (
0'
b0 $
0#
0"
b1100000111100010011101010101101001001011110010111111100010001110111011001011000101110110011110000101100100000001100110010100111011011011001011001000010111110010010101001010011001100011001110000101111011011100010100001101111000100011011001010010011001010100100110100000001011010010111100111001001100001100001010100101101100011101010011 !
$end
#1000000
1s
1t
1'
#2000000
0s
0t
0'
#3000000
1s
1t
1'
#4000000
0Y"
0a"
0i"
0q"
0##
0+#
03#
0;#
0J#
0s
0t
0'
1-
0k
1^
1,
#5000000
1K#
1]
1.
b1 (
1s
1t
1'
#6000000
0s
0t
0'
#7000000
1"
1\
b10 (
1s
1t
1'
#8000000
0s
0t
0'
#9000000
b11 (
b1 )
1s
1t
1'
#10000000
0s
0t
0'
#11000000
b10 )
b100 (
1s
1t
1'
#12000000
0s
0t
0'
#13000000
b101 (
b11 )
1s
1t
1'
#14000000
0s
0t
0'
#15000000
b100 )
b110 (
1s
1t
1'
#16000000
0s
0t
0'
#17000000
b111 (
b101 )
1s
1t
1'
#18000000
0s
0t
0'
#19000000
b110 )
b1000 (
1s
1t
1'
#20000000
0s
0t
0'
#21000000
b1001 (
b111 )
1s
1t
1'
#22000000
0s
0t
0'
#23000000
b1000 )
b1010 (
1s
1t
1'
#24000000
0s
0t
0'
#25000000
b1011 (
b1001 )
1s
1t
1'
#26000000
0s
0t
0'
#27000000
b1010 )
b1100 (
1s
1t
1'
#28000000
0s
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