diff --git a/0ctf/EzLogic/EzLogic.vvp b/0ctf/EzLogic/EzLogic.vvp new file mode 100644 index 0000000..9d8bc20 --- /dev/null +++ b/0ctf/EzLogic/EzLogic.vvp @@ -0,0 +1,1404 @@ +#! /c/Source/iverilog-install/bin/vvp +:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\system.vpi"; +:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\vhdl_sys.vpi"; +:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\vhdl_textio.vpi"; +:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\v2005_math.vpi"; +:vpi_module "C:\PROGRA~1\iverilog\lib\ivl\va_math.vpi"; +S_000001f7f2b9eb50 .scope module, "EzLogic_tb" "EzLogic_tb" 2 3; + .timescale -6 -7; +P_000001f7f2ae3ad0 .param/str "FLAG_TO_TEST" 0 2 4, "o0"; +P_000001f7f2ae3b08 .param/l "N" 0 2 5, +C4<00000000000000000000000000101010>; +v000001f7f2c1aa10_0 .var "clk", 0 0; +v000001f7f2c1a1f0_0 .var "counter", 6 0; +v000001f7f2c1bc30_0 .var "counter2", 6 0; +v000001f7f2c1c630_0 .var "data_in", 7 0; +v000001f7f2c1add0_0 .net "data_out", 7 0, L_000001f7f2c1a650; 1 drivers +v000001f7f2c1ac90_0 .var "data_out_all", 0 335; +L_000001f7f2c1f3c0 .functor BUFT 1, C4<001100000111100010011101010101101001001011110010111111100010001110111011001011000101110110011110000101100100000001100110010100111011011011001011001000010111110010010101001010011001100011001110000101111011011100010100001101111000100011011001010010011001010100100110100000001011010010111100111001001100001100001010100101101100011101010011>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1b550_0 .net "data_std", 0 335, L_000001f7f2c1f3c0; 1 drivers +L_000001f7f2c1eb50 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10 .array "flag_test_arr", 41 0; +v000001f7f2c1be10_0 .net v000001f7f2c1be10 0, 7 0, L_000001f7f2c1eb50; 1 drivers +L_000001f7f2c1eb08 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_1 .net v000001f7f2c1be10 1, 7 0, L_000001f7f2c1eb08; 1 drivers +L_000001f7f2c1eac0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_2 .net v000001f7f2c1be10 2, 7 0, L_000001f7f2c1eac0; 1 drivers +L_000001f7f2c1ea78 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_3 .net v000001f7f2c1be10 3, 7 0, L_000001f7f2c1ea78; 1 drivers +L_000001f7f2c1ea30 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_4 .net v000001f7f2c1be10 4, 7 0, L_000001f7f2c1ea30; 1 drivers +L_000001f7f2c1e9e8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_5 .net v000001f7f2c1be10 5, 7 0, L_000001f7f2c1e9e8; 1 drivers +L_000001f7f2c1e9a0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_6 .net v000001f7f2c1be10 6, 7 0, L_000001f7f2c1e9a0; 1 drivers +L_000001f7f2c1e958 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_7 .net v000001f7f2c1be10 7, 7 0, L_000001f7f2c1e958; 1 drivers +L_000001f7f2c1e910 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_8 .net v000001f7f2c1be10 8, 7 0, L_000001f7f2c1e910; 1 drivers +L_000001f7f2c1e8c8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_9 .net v000001f7f2c1be10 9, 7 0, L_000001f7f2c1e8c8; 1 drivers +L_000001f7f2c1e880 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_10 .net v000001f7f2c1be10 10, 7 0, L_000001f7f2c1e880; 1 drivers +L_000001f7f2c1e838 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_11 .net v000001f7f2c1be10 11, 7 0, L_000001f7f2c1e838; 1 drivers +L_000001f7f2c1e7f0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_12 .net v000001f7f2c1be10 12, 7 0, L_000001f7f2c1e7f0; 1 drivers +L_000001f7f2c1e7a8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_13 .net v000001f7f2c1be10 13, 7 0, L_000001f7f2c1e7a8; 1 drivers +L_000001f7f2c1e760 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_14 .net v000001f7f2c1be10 14, 7 0, L_000001f7f2c1e760; 1 drivers +L_000001f7f2c1e718 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_15 .net v000001f7f2c1be10 15, 7 0, L_000001f7f2c1e718; 1 drivers +L_000001f7f2c1e6d0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_16 .net v000001f7f2c1be10 16, 7 0, L_000001f7f2c1e6d0; 1 drivers +L_000001f7f2c1e688 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_17 .net v000001f7f2c1be10 17, 7 0, L_000001f7f2c1e688; 1 drivers +L_000001f7f2c1e640 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_18 .net v000001f7f2c1be10 18, 7 0, L_000001f7f2c1e640; 1 drivers +L_000001f7f2c1e5f8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_19 .net v000001f7f2c1be10 19, 7 0, L_000001f7f2c1e5f8; 1 drivers +L_000001f7f2c1e5b0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_20 .net v000001f7f2c1be10 20, 7 0, L_000001f7f2c1e5b0; 1 drivers +L_000001f7f2c1e568 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_21 .net v000001f7f2c1be10 21, 7 0, L_000001f7f2c1e568; 1 drivers +L_000001f7f2c1e520 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_22 .net v000001f7f2c1be10 22, 7 0, L_000001f7f2c1e520; 1 drivers +L_000001f7f2c1e4d8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_23 .net v000001f7f2c1be10 23, 7 0, L_000001f7f2c1e4d8; 1 drivers +L_000001f7f2c1e490 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_24 .net v000001f7f2c1be10 24, 7 0, L_000001f7f2c1e490; 1 drivers +L_000001f7f2c1e448 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_25 .net v000001f7f2c1be10 25, 7 0, L_000001f7f2c1e448; 1 drivers +L_000001f7f2c1e400 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_26 .net v000001f7f2c1be10 26, 7 0, L_000001f7f2c1e400; 1 drivers +L_000001f7f2c1e3b8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_27 .net v000001f7f2c1be10 27, 7 0, L_000001f7f2c1e3b8; 1 drivers +L_000001f7f2c1e370 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_28 .net v000001f7f2c1be10 28, 7 0, L_000001f7f2c1e370; 1 drivers +L_000001f7f2c1e328 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_29 .net v000001f7f2c1be10 29, 7 0, L_000001f7f2c1e328; 1 drivers +L_000001f7f2c1e2e0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_30 .net v000001f7f2c1be10 30, 7 0, L_000001f7f2c1e2e0; 1 drivers +L_000001f7f2c1e298 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_31 .net v000001f7f2c1be10 31, 7 0, L_000001f7f2c1e298; 1 drivers +L_000001f7f2c1e250 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_32 .net v000001f7f2c1be10 32, 7 0, L_000001f7f2c1e250; 1 drivers +L_000001f7f2c1e208 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_33 .net v000001f7f2c1be10 33, 7 0, L_000001f7f2c1e208; 1 drivers +L_000001f7f2c1e1c0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_34 .net v000001f7f2c1be10 34, 7 0, L_000001f7f2c1e1c0; 1 drivers +L_000001f7f2c1e178 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_35 .net v000001f7f2c1be10 35, 7 0, L_000001f7f2c1e178; 1 drivers +L_000001f7f2c1e130 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_36 .net v000001f7f2c1be10 36, 7 0, L_000001f7f2c1e130; 1 drivers +L_000001f7f2c1e0e8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_37 .net v000001f7f2c1be10 37, 7 0, L_000001f7f2c1e0e8; 1 drivers +L_000001f7f2c1e0a0 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_38 .net v000001f7f2c1be10 38, 7 0, L_000001f7f2c1e0a0; 1 drivers +L_000001f7f2c1e058 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_39 .net v000001f7f2c1be10 39, 7 0, L_000001f7f2c1e058; 1 drivers +L_000001f7f2c1e010 .functor BUFT 1, C4<01101111>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_40 .net v000001f7f2c1be10 40, 7 0, L_000001f7f2c1e010; 1 drivers +L_000001f7f2c1dfc8 .functor BUFT 1, C4<00110000>, C4<0>, C4<0>, C4<0>; +v000001f7f2c1be10_41 .net v000001f7f2c1be10 41, 7 0, L_000001f7f2c1dfc8; 1 drivers +v000001f7f2c1c450_0 .var "rst_n", 0 0; +v000001f7f2c1b7d0_0 .var "start", 0 0; +v000001f7f2c1ae70_0 .net "success", 0 0, L_000001f7f2c67c20; 1 drivers +v000001f7f2c1b5f0_0 .var "valid_in", 0 0; +v000001f7f2c1b190_0 .net "valid_out", 0 0, L_000001f7f2c6f520; 1 drivers +E_000001f7f2b95b20 .event posedge, v000001f7f2b98740_0; +E_000001f7f2b95560 .event negedge, v000001f7f2c1b7d0_0; +L_000001f7f2c67c20 .cmp/eq 336, L_000001f7f2c1f3c0, v000001f7f2c1ac90_0; +S_000001f7f2ba25e0 .scope generate, "genblk1[0]" "genblk1[0]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b95be0 .param/l "i" 0 2 22, +C4<00>; +S_000001f7f2ba3720 .scope generate, "genblk1[1]" "genblk1[1]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b957e0 .param/l "i" 0 2 22, +C4<01>; +S_000001f7f2b218a0 .scope generate, "genblk1[2]" "genblk1[2]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b96120 .param/l "i" 0 2 22, +C4<010>; +S_000001f7f2b21a30 .scope generate, "genblk1[3]" "genblk1[3]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b95d20 .param/l "i" 0 2 22, +C4<011>; +S_000001f7f2b20410 .scope generate, "genblk1[4]" "genblk1[4]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b95f20 .param/l "i" 0 2 22, +C4<0100>; +S_000001f7f2b205a0 .scope generate, "genblk1[5]" "genblk1[5]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b96420 .param/l "i" 0 2 22, +C4<0101>; +S_000001f7f2b1a660 .scope generate, "genblk1[6]" "genblk1[6]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b95ea0 .param/l "i" 0 2 22, +C4<0110>; +S_000001f7f2b1a7f0 .scope generate, "genblk1[7]" "genblk1[7]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b96060 .param/l "i" 0 2 22, +C4<0111>; +S_000001f7f2b191d0 .scope generate, "genblk1[8]" "genblk1[8]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b95ee0 .param/l "i" 0 2 22, +C4<01000>; +S_000001f7f2b19360 .scope generate, "genblk1[9]" "genblk1[9]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b96360 .param/l "i" 0 2 22, +C4<01001>; +S_000001f7f2b13d20 .scope generate, "genblk1[10]" "genblk1[10]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b96220 .param/l "i" 0 2 22, +C4<01010>; +S_000001f7f2b13eb0 .scope generate, "genblk1[11]" "genblk1[11]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b955a0 .param/l "i" 0 2 22, +C4<01011>; +S_000001f7f2b133e0 .scope generate, "genblk1[12]" "genblk1[12]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b963a0 .param/l "i" 0 2 22, +C4<01100>; +S_000001f7f2b13570 .scope generate, "genblk1[13]" "genblk1[13]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92560 .param/l "i" 0 2 22, +C4<01101>; +S_000001f7f2b12eb0 .scope generate, "genblk1[14]" "genblk1[14]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92720 .param/l "i" 0 2 22, +C4<01110>; +S_000001f7f2b13040 .scope generate, "genblk1[15]" "genblk1[15]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92aa0 .param/l "i" 0 2 22, +C4<01111>; +S_000001f7f2ba4670 .scope generate, "genblk1[16]" "genblk1[16]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92f60 .param/l "i" 0 2 22, +C4<010000>; +S_000001f7f2ba3ea0 .scope generate, "genblk1[17]" "genblk1[17]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92be0 .param/l "i" 0 2 22, +C4<010001>; +S_000001f7f2ba4030 .scope generate, "genblk1[18]" "genblk1[18]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b926e0 .param/l "i" 0 2 22, +C4<010010>; +S_000001f7f2ba41c0 .scope generate, "genblk1[19]" "genblk1[19]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92760 .param/l "i" 0 2 22, +C4<010011>; +S_000001f7f2ba4350 .scope generate, "genblk1[20]" "genblk1[20]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b929e0 .param/l "i" 0 2 22, +C4<010100>; +S_000001f7f2ba4b20 .scope generate, "genblk1[21]" "genblk1[21]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92d20 .param/l "i" 0 2 22, +C4<010101>; +S_000001f7f2ba4990 .scope generate, "genblk1[22]" "genblk1[22]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b93320 .param/l "i" 0 2 22, +C4<010110>; +S_000001f7f2ba44e0 .scope generate, "genblk1[23]" "genblk1[23]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b927a0 .param/l "i" 0 2 22, +C4<010111>; +S_000001f7f2ba4800 .scope generate, "genblk1[24]" "genblk1[24]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b931a0 .param/l "i" 0 2 22, +C4<011000>; +S_000001f7f2ba4cb0 .scope generate, "genblk1[25]" "genblk1[25]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92ae0 .param/l "i" 0 2 22, +C4<011001>; +S_000001f7f2ba5360 .scope generate, "genblk1[26]" "genblk1[26]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b933e0 .param/l "i" 0 2 22, +C4<011010>; +S_000001f7f2ba67b0 .scope generate, "genblk1[27]" "genblk1[27]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b93160 .param/l "i" 0 2 22, +C4<011011>; +S_000001f7f2ba5fe0 .scope generate, "genblk1[28]" "genblk1[28]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b933a0 .param/l "i" 0 2 22, +C4<011100>; +S_000001f7f2ba5810 .scope generate, "genblk1[29]" "genblk1[29]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b931e0 .param/l "i" 0 2 22, +C4<011101>; +S_000001f7f2ba59a0 .scope generate, "genblk1[30]" "genblk1[30]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b93360 .param/l "i" 0 2 22, +C4<011110>; +S_000001f7f2ba5cc0 .scope generate, "genblk1[31]" "genblk1[31]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92e60 .param/l "i" 0 2 22, +C4<011111>; +S_000001f7f2ba6940 .scope generate, "genblk1[32]" "genblk1[32]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92b20 .param/l "i" 0 2 22, +C4<0100000>; +S_000001f7f2ba54f0 .scope generate, "genblk1[33]" "genblk1[33]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92620 .param/l "i" 0 2 22, +C4<0100001>; +S_000001f7f2ba6620 .scope generate, "genblk1[34]" "genblk1[34]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92820 .param/l "i" 0 2 22, +C4<0100010>; +S_000001f7f2ba5680 .scope generate, "genblk1[35]" "genblk1[35]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b929a0 .param/l "i" 0 2 22, +C4<0100011>; +S_000001f7f2ba4eb0 .scope generate, "genblk1[36]" "genblk1[36]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92b60 .param/l "i" 0 2 22, +C4<0100100>; +S_000001f7f2ba5040 .scope generate, "genblk1[37]" "genblk1[37]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92660 .param/l "i" 0 2 22, +C4<0100101>; +S_000001f7f2ba5e50 .scope generate, "genblk1[38]" "genblk1[38]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b93120 .param/l "i" 0 2 22, +C4<0100110>; +S_000001f7f2ba51d0 .scope generate, "genblk1[39]" "genblk1[39]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92e20 .param/l "i" 0 2 22, +C4<0100111>; +S_000001f7f2ba6170 .scope generate, "genblk1[40]" "genblk1[40]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92fa0 .param/l "i" 0 2 22, +C4<0101000>; +S_000001f7f2ba6ad0 .scope generate, "genblk1[41]" "genblk1[41]" 2 22, 2 22 0, S_000001f7f2b9eb50; + .timescale -6 -7; +P_000001f7f2b92860 .param/l "i" 0 2 22, +C4<0101001>; +S_000001f7f2ba6300 .scope module, "inst" "EzLogic_top" 2 27, 3 16 0, S_000001f7f2b9eb50; + .timescale -12 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst_n"; + .port_info 2 /INPUT 8 "data_in"; + .port_info 3 /INPUT 1 "valid_in"; + .port_info 4 /OUTPUT 8 "data_out"; + .port_info 5 /OUTPUT 1 "valid_out"; +L_000001f7f2c1eb98 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v000001f7f2c192b0_0 .net "", 0 0, L_000001f7f2c1eb98; 1 drivers +L_000001f7f2c1ebe0 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v000001f7f2c19850_0 .net "", 0 0, L_000001f7f2c1ebe0; 1 drivers +v000001f7f2c19a30_0 .net *"_ivl_115", 0 0, L_000001f7f2c6ae20; 1 drivers +v000001f7f2c19ad0_0 .net *"_ivl_117", 0 0, L_000001f7f2c69840; 1 drivers +v000001f7f2c19c10_0 .net *"_ivl_119", 0 0, L_000001f7f2c6a2e0; 1 drivers +v000001f7f2c18630_0 .net *"_ivl_121", 0 0, L_000001f7f2c6a380; 1 drivers +v000001f7f2c18d10_0 .net *"_ivl_151", 0 0, L_000001f7f2c69f20; 1 drivers +v000001f7f2c18db0_0 .net *"_ivl_153", 0 0, L_000001f7f2c6a880; 1 drivers +v000001f7f2c18e50_0 .net *"_ivl_155", 0 0, L_000001f7f2c6a9c0; 1 drivers +v000001f7f2c18ef0_0 .net *"_ivl_160", 2 0, L_000001f7f2c68da0; 1 drivers +v000001f7f2c18f90_0 .net "clk", 0 0, v000001f7f2c1aa10_0; 1 drivers +v000001f7f2c19030_0 .net "clk_IBUF", 0 0, L_000001f7f2b86510; 1 drivers +v000001f7f2c190d0_0 .net "clk_IBUF_BUFG", 0 0, L_000001f7f2b864a0; 1 drivers +v000001f7f2c19170_0 .net "data_in", 7 0, v000001f7f2c1c630_0; 1 drivers +v000001f7f2c19210_0 .net "data_in_IBUF", 7 0, L_000001f7f2c1b730; 1 drivers +v000001f7f2c193f0_0 .net "data_out", 7 0, L_000001f7f2c1a650; alias, 1 drivers +v000001f7f2c19490_0 .net "data_out_OBUF", 7 0, L_000001f7f2c69a20; 1 drivers +v000001f7f2c1a8d0_0 .net "data_reg[3]_i_2_n_0", 0 0, L_000001f7f2c1c1d0; 1 drivers +v000001f7f2c1c310_0 .net "data_reg[3]_i_3_n_0", 0 0, L_000001f7f2c1b690; 1 drivers +v000001f7f2c1c3b0_0 .net "data_reg[3]_i_4_n_0", 0 0, L_000001f7f2c1bf50; 1 drivers +v000001f7f2c1b910_0 .net "data_reg[3]_i_5_n_0", 0 0, L_000001f7f2c1d530; 1 drivers +v000001f7f2c1afb0_0 .net "data_reg[7]_i_2_n_0", 0 0, L_000001f7f2c1c9f0; 1 drivers +v000001f7f2c1a970_0 .net "data_reg[7]_i_3_n_0", 0 0, L_000001f7f2c1d170; 1 drivers +v000001f7f2c1a830_0 .net "data_reg[7]_i_4_n_0", 0 0, L_000001f7f2c1d210; 1 drivers +v000001f7f2c1a5b0_0 .net "data_reg[7]_i_5_n_0", 0 0, L_000001f7f2c1cdb0; 1 drivers +v000001f7f2c1aab0_0 .net "data_reg[7]_i_6_n_0", 0 0, L_000001f7f2c1c810; 1 drivers +v000001f7f2c1b870_0 .net "data_reg_reg[3]_i_1_n_0", 0 0, L_000001f7f2c69c00; 1 drivers +v000001f7f2c1ad30_0 .net "data_reg_reg[3]_i_1_n_1", 0 0, L_000001f7f2c6ac40; 1 drivers +v000001f7f2c1ab50_0 .net "data_reg_reg[3]_i_1_n_2", 0 0, L_000001f7f2c6ad80; 1 drivers +v000001f7f2c1c770_0 .net "data_reg_reg[3]_i_1_n_3", 0 0, L_000001f7f2c69ac0; 1 drivers +v000001f7f2c1c270_0 .net "data_reg_reg[7]_i_1_n_1", 0 0, L_000001f7f2c67680; 1 drivers +v000001f7f2c1a010_0 .net "data_reg_reg[7]_i_1_n_2", 0 0, L_000001f7f2c67900; 1 drivers +v000001f7f2c1a790_0 .net "data_reg_reg[7]_i_1_n_3", 0 0, L_000001f7f2c67860; 1 drivers +v000001f7f2c1a150_0 .net "p_0_in", 7 0, L_000001f7f2c67fe0; 1 drivers +v000001f7f2c1c6d0_0 .net "rst_n", 0 0, v000001f7f2c1c450_0; 1 drivers +v000001f7f2c1b9b0_0 .net "rst_n_IBUF", 0 0, L_000001f7f2c6f440; 1 drivers +v000001f7f2c1b050_0 .net "valid_in", 0 0, v000001f7f2c1b5f0_0; 1 drivers +v000001f7f2c1abf0_0 .net "valid_in_IBUF", 0 0, L_000001f7f2c6fb40; 1 drivers +v000001f7f2c1b0f0_0 .net "valid_out", 0 0, L_000001f7f2c6f520; alias, 1 drivers +v000001f7f2c1b2d0_0 .net "valid_out_OBUF", 0 0, v000001f7f2c183b0_0; 1 drivers +L_000001f7f2c1bb90 .part v000001f7f2c1c630_0, 0, 1; +L_000001f7f2c1af10 .part v000001f7f2c1c630_0, 1, 1; +L_000001f7f2c1a330 .part v000001f7f2c1c630_0, 2, 1; +L_000001f7f2c1b230 .part v000001f7f2c1c630_0, 3, 1; +L_000001f7f2c1c590 .part v000001f7f2c1c630_0, 4, 1; +L_000001f7f2c1a0b0 .part v000001f7f2c1c630_0, 5, 1; +L_000001f7f2c1bff0 .part v000001f7f2c1c630_0, 6, 1; +L_000001f7f2c1ba50 .part v000001f7f2c1c630_0, 7, 1; +LS_000001f7f2c1b730_0_0 .concat8 [ 1 1 1 1], L_000001f7f2b866d0, L_000001f7f2b86970, L_000001f7f2b86580, L_000001f7f2b87000; +LS_000001f7f2c1b730_0_4 .concat8 [ 1 1 1 1], L_000001f7f2b87230, L_000001f7f2b865f0, L_000001f7f2b86740, L_000001f7f2b867b0; +L_000001f7f2c1b730 .concat8 [ 4 4 0 0], LS_000001f7f2c1b730_0_0, LS_000001f7f2c1b730_0_4; +L_000001f7f2c1b370 .part L_000001f7f2c69a20, 0, 1; +L_000001f7f2c1baf0 .part L_000001f7f2c69a20, 1, 1; +L_000001f7f2c1c090 .part L_000001f7f2c69a20, 2, 1; +L_000001f7f2c1a290 .part L_000001f7f2c69a20, 3, 1; +L_000001f7f2c1a3d0 .part L_000001f7f2c69a20, 4, 1; +L_000001f7f2c1a470 .part L_000001f7f2c69a20, 5, 1; +L_000001f7f2c1bcd0 .part L_000001f7f2c69a20, 6, 1; +L_000001f7f2c1c130 .part L_000001f7f2c69a20, 7, 1; +LS_000001f7f2c1a650_0_0 .concat8 [ 1 1 1 1], L_000001f7f2b86890, L_000001f7f2c66e90, L_000001f7f2c66020, L_000001f7f2c66330; +LS_000001f7f2c1a650_0_4 .concat8 [ 1 1 1 1], L_000001f7f2c66cd0, L_000001f7f2c663a0, L_000001f7f2c66870, L_000001f7f2c66f00; +L_000001f7f2c1a650 .concat8 [ 4 4 0 0], LS_000001f7f2c1a650_0_0, LS_000001f7f2c1a650_0_4; +L_000001f7f2c1c4f0 .part L_000001f7f2c69a20, 5, 1; +L_000001f7f2c1b410 .part L_000001f7f2c1b730, 3, 1; +L_000001f7f2c1beb0 .part L_000001f7f2c69a20, 6, 1; +L_000001f7f2c1a6f0 .part L_000001f7f2c1b730, 2, 1; +L_000001f7f2c1d670 .part L_000001f7f2c69a20, 2, 1; +L_000001f7f2c1d0d0 .part L_000001f7f2c1b730, 1, 1; +L_000001f7f2c1de90 .part L_000001f7f2c69a20, 4, 1; +L_000001f7f2c1dc10 .part L_000001f7f2c1b730, 0, 1; +L_000001f7f2c1d2b0 .part L_000001f7f2c69a20, 7, 1; +L_000001f7f2c1d5d0 .part L_000001f7f2c1b730, 7, 1; +L_000001f7f2c1d850 .part L_000001f7f2c69a20, 0, 1; +L_000001f7f2c1dd50 .part L_000001f7f2c1b730, 6, 1; +L_000001f7f2c1d8f0 .part L_000001f7f2c69a20, 3, 1; +L_000001f7f2c1cb30 .part L_000001f7f2c1b730, 5, 1; +L_000001f7f2c1d030 .part L_000001f7f2c69a20, 1, 1; +L_000001f7f2c1c950 .part L_000001f7f2c1b730, 4, 1; +L_000001f7f2c1ce50 .part L_000001f7f2c67fe0, 0, 1; +L_000001f7f2c1ca90 .part L_000001f7f2c67fe0, 1, 1; +L_000001f7f2c1d7b0 .part L_000001f7f2c67fe0, 2, 1; +L_000001f7f2c1cbd0 .part L_000001f7f2c67fe0, 3, 1; +L_000001f7f2c6ae20 .part L_000001f7f2c69a20, 5, 1; +L_000001f7f2c69840 .part L_000001f7f2c69a20, 6, 1; +L_000001f7f2c6a2e0 .part L_000001f7f2c69a20, 2, 1; +L_000001f7f2c6a380 .part L_000001f7f2c69a20, 4, 1; +L_000001f7f2c698e0 .concat [ 1 1 1 1], L_000001f7f2c6a380, L_000001f7f2c6a2e0, L_000001f7f2c69840, L_000001f7f2c6ae20; +L_000001f7f2c6a100 .concat [ 1 1 1 1], L_000001f7f2c1d530, L_000001f7f2c1bf50, L_000001f7f2c1b690, L_000001f7f2c1c1d0; +L_000001f7f2c69c00 .part L_000001f7f2c6a4c0, 3, 1; +L_000001f7f2c6ac40 .part L_000001f7f2c6a4c0, 2, 1; +L_000001f7f2c6ad80 .part L_000001f7f2c6a4c0, 1, 1; +L_000001f7f2c69ac0 .part L_000001f7f2c6a4c0, 0, 1; +L_000001f7f2c69fc0 .part L_000001f7f2c67fe0, 4, 1; +L_000001f7f2c69980 .part L_000001f7f2c67fe0, 5, 1; +L_000001f7f2c6a740 .part L_000001f7f2c67fe0, 6, 1; +L_000001f7f2c6a240 .part L_000001f7f2c67fe0, 7, 1; +LS_000001f7f2c69a20_0_0 .concat8 [ 1 1 1 1], v000001f7f2c13320_0, v000001f7f2c13b40_0, v000001f7f2c12ba0_0, v000001f7f2c129c0_0; +LS_000001f7f2c69a20_0_4 .concat8 [ 1 1 1 1], v000001f7f2c15b50_0, v000001f7f2c14250_0, v000001f7f2c14430_0, v000001f7f2c15510_0; +L_000001f7f2c69a20 .concat8 [ 4 4 0 0], LS_000001f7f2c69a20_0_0, LS_000001f7f2c69a20_0_4; +L_000001f7f2c69f20 .part L_000001f7f2c69a20, 0, 1; +L_000001f7f2c6a880 .part L_000001f7f2c69a20, 3, 1; +L_000001f7f2c6a9c0 .part L_000001f7f2c69a20, 1, 1; +L_000001f7f2c6aba0 .concat [ 1 1 1 1], L_000001f7f2c6a9c0, L_000001f7f2c6a880, L_000001f7f2c69f20, L_000001f7f2c1eb98; +L_000001f7f2c677c0 .concat [ 1 1 1 1], L_000001f7f2c1c810, L_000001f7f2c1cdb0, L_000001f7f2c1d210, L_000001f7f2c1d170; +L_000001f7f2c67680 .part L_000001f7f2c68da0, 2, 1; +L_000001f7f2c67900 .part L_000001f7f2c68da0, 1, 1; +L_000001f7f2c67860 .part L_000001f7f2c68da0, 0, 1; +L_000001f7f2c68da0 .part L_000001f7f2c6aa60, 0, 3; +L_000001f7f2c67fe0 .concat8 [ 4 4 0 0], L_000001f7f2c666b0, L_000001f7f2c6fde0; +S_000001f7f2ba5b30 .scope module, "GND" "GND" 3 63, 4 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /OUTPUT 1 "G"; +v000001f7f2b99960_0 .net "G", 0 0, L_000001f7f2c1eb98; alias, 1 drivers +S_000001f7f2ba6c60 .scope module, "VCC" "VCC" 3 65, 5 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /OUTPUT 1 "P"; +v000001f7f2b99c80_0 .net "P", 0 0, L_000001f7f2c1ebe0; alias, 1 drivers +S_000001f7f2ba6490 .scope module, "clk_IBUF_BUFG_inst" "BUFG" 3 67, 6 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b864a0 .functor BUFZ 1, L_000001f7f2b86510, C4<0>, C4<0>, C4<0>; +v000001f7f2b98b00_0 .net "I", 0 0, L_000001f7f2b86510; alias, 1 drivers +v000001f7f2b9a180_0 .net "O", 0 0, L_000001f7f2b864a0; alias, 1 drivers +S_000001f7f2c08d90 .scope module, "clk_IBUF_inst" "IBUF" 3 70, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b86510 .functor BUFZ 1, v000001f7f2c1aa10_0, C4<0>, C4<0>, C4<0>; +v000001f7f2b98740_0 .net "I", 0 0, v000001f7f2c1aa10_0; alias, 1 drivers +v000001f7f2b98c40_0 .net "O", 0 0, L_000001f7f2b86510; alias, 1 drivers +S_000001f7f2c082a0 .scope module, "data_in_IBUF[0]_inst" "IBUF" 3 73, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b866d0 .functor BUFZ 1, L_000001f7f2c1bb90, C4<0>, C4<0>, C4<0>; +v000001f7f2b99460_0 .net "I", 0 0, L_000001f7f2c1bb90; 1 drivers +v000001f7f2b99aa0_0 .net "O", 0 0, L_000001f7f2b866d0; 1 drivers +S_000001f7f2c08750 .scope module, "data_in_IBUF[1]_inst" "IBUF" 3 76, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b86970 .functor BUFZ 1, L_000001f7f2c1af10, C4<0>, C4<0>, C4<0>; +v000001f7f2b990a0_0 .net "I", 0 0, L_000001f7f2c1af10; 1 drivers +v000001f7f2b99a00_0 .net "O", 0 0, L_000001f7f2b86970; 1 drivers +S_000001f7f2c09240 .scope module, "data_in_IBUF[2]_inst" "IBUF" 3 79, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b86580 .functor BUFZ 1, L_000001f7f2c1a330, C4<0>, C4<0>, C4<0>; +v000001f7f2b9a2c0_0 .net "I", 0 0, L_000001f7f2c1a330; 1 drivers +v000001f7f2b99780_0 .net "O", 0 0, L_000001f7f2b86580; 1 drivers +S_000001f7f2c088e0 .scope module, "data_in_IBUF[3]_inst" "IBUF" 3 82, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b87000 .functor BUFZ 1, L_000001f7f2c1b230, C4<0>, C4<0>, C4<0>; +v000001f7f2b98a60_0 .net "I", 0 0, L_000001f7f2c1b230; 1 drivers +v000001f7f2b99140_0 .net "O", 0 0, L_000001f7f2b87000; 1 drivers +S_000001f7f2c09560 .scope module, "data_in_IBUF[4]_inst" "IBUF" 3 85, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b87230 .functor BUFZ 1, L_000001f7f2c1c590, C4<0>, C4<0>, C4<0>; +v000001f7f2b989c0_0 .net "I", 0 0, L_000001f7f2c1c590; 1 drivers +v000001f7f2b99fa0_0 .net "O", 0 0, L_000001f7f2b87230; 1 drivers +S_000001f7f2c090b0 .scope module, "data_in_IBUF[5]_inst" "IBUF" 3 88, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b865f0 .functor BUFZ 1, L_000001f7f2c1a0b0, C4<0>, C4<0>, C4<0>; +v000001f7f2b986a0_0 .net "I", 0 0, L_000001f7f2c1a0b0; 1 drivers +v000001f7f2b9a220_0 .net "O", 0 0, L_000001f7f2b865f0; 1 drivers +S_000001f7f2c093d0 .scope module, "data_in_IBUF[6]_inst" "IBUF" 3 91, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b86740 .functor BUFZ 1, L_000001f7f2c1bff0, C4<0>, C4<0>, C4<0>; +v000001f7f2b98ce0_0 .net "I", 0 0, L_000001f7f2c1bff0; 1 drivers +v000001f7f2b98560_0 .net "O", 0 0, L_000001f7f2b86740; 1 drivers +S_000001f7f2c096f0 .scope module, "data_in_IBUF[7]_inst" "IBUF" 3 94, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b867b0 .functor BUFZ 1, L_000001f7f2c1ba50, C4<0>, C4<0>, C4<0>; +v000001f7f2b98920_0 .net "I", 0 0, L_000001f7f2c1ba50; 1 drivers +v000001f7f2b98e20_0 .net "O", 0 0, L_000001f7f2b867b0; 1 drivers +S_000001f7f2c08f20 .scope module, "data_out_OBUF[0]_inst" "OBUF" 3 97, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2b86890 .functor BUFZ 1, L_000001f7f2c1b370, C4<0>, C4<0>, C4<0>; +v000001f7f2b99000_0 .net "I", 0 0, L_000001f7f2c1b370; 1 drivers +v000001f7f2b996e0_0 .net "O", 0 0, L_000001f7f2b86890; 1 drivers +S_000001f7f2c09a10 .scope module, "data_out_OBUF[1]_inst" "OBUF" 3 100, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c66e90 .functor BUFZ 1, L_000001f7f2c1baf0, C4<0>, C4<0>, C4<0>; +v000001f7f2b98d80_0 .net "I", 0 0, L_000001f7f2c1baf0; 1 drivers +v000001f7f2b98ec0_0 .net "O", 0 0, L_000001f7f2c66e90; 1 drivers +S_000001f7f2c09880 .scope module, "data_out_OBUF[2]_inst" "OBUF" 3 103, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c66020 .functor BUFZ 1, L_000001f7f2c1c090, C4<0>, C4<0>, C4<0>; +v000001f7f2b99dc0_0 .net "I", 0 0, L_000001f7f2c1c090; 1 drivers +v000001f7f2b9a0e0_0 .net "O", 0 0, L_000001f7f2c66020; 1 drivers +S_000001f7f2c09ba0 .scope module, "data_out_OBUF[3]_inst" "OBUF" 3 106, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c66330 .functor BUFZ 1, L_000001f7f2c1a290, C4<0>, C4<0>, C4<0>; +v000001f7f2b991e0_0 .net "I", 0 0, L_000001f7f2c1a290; 1 drivers +v000001f7f2b9a360_0 .net "O", 0 0, L_000001f7f2c66330; 1 drivers +S_000001f7f2c08110 .scope module, "data_out_OBUF[4]_inst" "OBUF" 3 109, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c66cd0 .functor BUFZ 1, L_000001f7f2c1a3d0, C4<0>, C4<0>, C4<0>; +v000001f7f2b99280_0 .net "I", 0 0, L_000001f7f2c1a3d0; 1 drivers +v000001f7f2b99320_0 .net "O", 0 0, L_000001f7f2c66cd0; 1 drivers +S_000001f7f2c08a70 .scope module, "data_out_OBUF[5]_inst" "OBUF" 3 111, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c663a0 .functor BUFZ 1, L_000001f7f2c1a470, C4<0>, C4<0>, C4<0>; +v000001f7f2b99500_0 .net "I", 0 0, L_000001f7f2c1a470; 1 drivers +v000001f7f2b995a0_0 .net "O", 0 0, L_000001f7f2c663a0; 1 drivers +S_000001f7f2c09d30 .scope module, "data_out_OBUF[6]_inst" "OBUF" 3 114, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c66870 .functor BUFZ 1, L_000001f7f2c1bcd0, C4<0>, C4<0>, C4<0>; +v000001f7f2b99640_0 .net "I", 0 0, L_000001f7f2c1bcd0; 1 drivers +v000001f7f2b86070_0 .net "O", 0 0, L_000001f7f2c66870; 1 drivers +S_000001f7f2c07f80 .scope module, "data_out_OBUF[7]_inst" "OBUF" 3 117, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c66f00 .functor BUFZ 1, L_000001f7f2c1c130, C4<0>, C4<0>, C4<0>; +v000001f7f2c0b1b0_0 .net "I", 0 0, L_000001f7f2c1c130; 1 drivers +v000001f7f2c0bc50_0 .net "O", 0 0, L_000001f7f2c66f00; 1 drivers +S_000001f7f2c08430 .scope module, "data_reg[3]_i_2" "LUT2" 3 122, 9 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /INPUT 1 "I1"; + .port_info 2 /OUTPUT 1 "O"; +P_000001f7f2b92c60 .param/l "INIT" 0 9 15, C4<0110>; +v000001f7f2c0bb10_0 .net "I0", 0 0, L_000001f7f2c1c4f0; 1 drivers +v000001f7f2c0b2f0_0 .net "I1", 0 0, L_000001f7f2c1b410; 1 drivers +v000001f7f2c0b610_0 .net "O", 0 0, L_000001f7f2c1c1d0; alias, 1 drivers +L_000001f7f2c1ec28 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0b6b0_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ec28; 1 drivers +v000001f7f2c0bbb0_0 .net "_w_idx", 1 0, L_000001f7f2c1a510; 1 drivers +L_000001f7f2c1a510 .concat [ 1 1 0 0], L_000001f7f2c1c4f0, L_000001f7f2c1b410; +L_000001f7f2c1c1d0 .part/v L_000001f7f2c1ec28, L_000001f7f2c1a510, 1; +S_000001f7f2c08c00 .scope module, "data_reg[3]_i_3" "LUT2" 3 128, 9 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /INPUT 1 "I1"; + .port_info 2 /OUTPUT 1 "O"; +P_000001f7f2b934a0 .param/l "INIT" 0 9 15, C4<0110>; +v000001f7f2c0be30_0 .net "I0", 0 0, L_000001f7f2c1beb0; 1 drivers +v000001f7f2c09f90_0 .net "I1", 0 0, L_000001f7f2c1a6f0; 1 drivers +v000001f7f2c0bcf0_0 .net "O", 0 0, L_000001f7f2c1b690; alias, 1 drivers +L_000001f7f2c1ec70 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0b750_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ec70; 1 drivers +v000001f7f2c0a170_0 .net "_w_idx", 1 0, L_000001f7f2c1b4b0; 1 drivers +L_000001f7f2c1b4b0 .concat [ 1 1 0 0], L_000001f7f2c1beb0, L_000001f7f2c1a6f0; +L_000001f7f2c1b690 .part/v L_000001f7f2c1ec70, L_000001f7f2c1b4b0, 1; +S_000001f7f2c085c0 .scope module, "data_reg[3]_i_4" "LUT2" 3 134, 9 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /INPUT 1 "I1"; + .port_info 2 /OUTPUT 1 "O"; +P_000001f7f2b93220 .param/l "INIT" 0 9 15, C4<0110>; +v000001f7f2c0ac10_0 .net "I0", 0 0, L_000001f7f2c1d670; 1 drivers +v000001f7f2c0a670_0 .net "I1", 0 0, L_000001f7f2c1d0d0; 1 drivers +v000001f7f2c0a030_0 .net "O", 0 0, L_000001f7f2c1bf50; alias, 1 drivers +L_000001f7f2c1ecb8 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0b390_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ecb8; 1 drivers +v000001f7f2c0b890_0 .net "_w_idx", 1 0, L_000001f7f2c1bd70; 1 drivers +L_000001f7f2c1bd70 .concat [ 1 1 0 0], L_000001f7f2c1d670, L_000001f7f2c1d0d0; +L_000001f7f2c1bf50 .part/v L_000001f7f2c1ecb8, L_000001f7f2c1bd70, 1; +S_000001f7f2c10460 .scope module, "data_reg[3]_i_5" "LUT2" 3 140, 9 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /INPUT 1 "I1"; + .port_info 2 /OUTPUT 1 "O"; +P_000001f7f2b926a0 .param/l "INIT" 0 9 15, C4<0110>; +v000001f7f2c0a2b0_0 .net "I0", 0 0, L_000001f7f2c1de90; 1 drivers +v000001f7f2c0aa30_0 .net "I1", 0 0, L_000001f7f2c1dc10; 1 drivers +v000001f7f2c0af30_0 .net "O", 0 0, L_000001f7f2c1d530; alias, 1 drivers +L_000001f7f2c1ed00 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0bd90_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ed00; 1 drivers +v000001f7f2c0b7f0_0 .net "_w_idx", 1 0, L_000001f7f2c1cc70; 1 drivers +L_000001f7f2c1cc70 .concat [ 1 1 0 0], L_000001f7f2c1de90, L_000001f7f2c1dc10; +L_000001f7f2c1d530 .part/v L_000001f7f2c1ed00, L_000001f7f2c1cc70, 1; +S_000001f7f2c118b0 .scope module, "data_reg[7]_i_2" "LUT1" 3 146, 10 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /OUTPUT 1 "O"; +P_000001f7f2b930a0 .param/l "INIT" 0 10 15, C4<01>; +v000001f7f2c0ae90_0 .net "I0", 0 0, L_000001f7f2c6f440; alias, 1 drivers +v000001f7f2c0a710_0 .net "O", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +L_000001f7f2c1ed48 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0a990_0 .net/2u *"_ivl_0", 1 0, L_000001f7f2c1ed48; 1 drivers +L_000001f7f2c1c9f0 .part/v L_000001f7f2c1ed48, L_000001f7f2c6f440, 1; +S_000001f7f2c110e0 .scope module, "data_reg[7]_i_3" "LUT2" 3 151, 9 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /INPUT 1 "I1"; + .port_info 2 /OUTPUT 1 "O"; +P_000001f7f2b93060 .param/l "INIT" 0 9 15, C4<0110>; +v000001f7f2c0ba70_0 .net "I0", 0 0, L_000001f7f2c1d2b0; 1 drivers +v000001f7f2c0a3f0_0 .net "I1", 0 0, L_000001f7f2c1d5d0; 1 drivers +v000001f7f2c0a0d0_0 .net "O", 0 0, L_000001f7f2c1d170; alias, 1 drivers +L_000001f7f2c1ed90 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0a530_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ed90; 1 drivers +v000001f7f2c0b250_0 .net "_w_idx", 1 0, L_000001f7f2c1c8b0; 1 drivers +L_000001f7f2c1c8b0 .concat [ 1 1 0 0], L_000001f7f2c1d2b0, L_000001f7f2c1d5d0; +L_000001f7f2c1d170 .part/v L_000001f7f2c1ed90, L_000001f7f2c1c8b0, 1; +S_000001f7f2c0ffb0 .scope module, "data_reg[7]_i_4" "LUT2" 3 157, 9 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /INPUT 1 "I1"; + .port_info 2 /OUTPUT 1 "O"; +P_000001f7f2b93260 .param/l "INIT" 0 9 15, C4<0110>; +v000001f7f2c0a210_0 .net "I0", 0 0, L_000001f7f2c1d850; 1 drivers +v000001f7f2c0a350_0 .net "I1", 0 0, L_000001f7f2c1dd50; 1 drivers +v000001f7f2c0a490_0 .net "O", 0 0, L_000001f7f2c1d210; alias, 1 drivers +L_000001f7f2c1edd8 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0b930_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1edd8; 1 drivers +v000001f7f2c0aad0_0 .net "_w_idx", 1 0, L_000001f7f2c1dcb0; 1 drivers +L_000001f7f2c1dcb0 .concat [ 1 1 0 0], L_000001f7f2c1d850, L_000001f7f2c1dd50; +L_000001f7f2c1d210 .part/v L_000001f7f2c1edd8, L_000001f7f2c1dcb0, 1; +S_000001f7f2c11400 .scope module, "data_reg[7]_i_5" "LUT2" 3 163, 9 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /INPUT 1 "I1"; + .port_info 2 /OUTPUT 1 "O"; +P_000001f7f2b92ca0 .param/l "INIT" 0 9 15, C4<0110>; +v000001f7f2c0a5d0_0 .net "I0", 0 0, L_000001f7f2c1d8f0; 1 drivers +v000001f7f2c0b9d0_0 .net "I1", 0 0, L_000001f7f2c1cb30; 1 drivers +v000001f7f2c0a7b0_0 .net "O", 0 0, L_000001f7f2c1cdb0; alias, 1 drivers +L_000001f7f2c1ee20 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0b110_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ee20; 1 drivers +v000001f7f2c0ad50_0 .net "_w_idx", 1 0, L_000001f7f2c1ddf0; 1 drivers +L_000001f7f2c1ddf0 .concat [ 1 1 0 0], L_000001f7f2c1d8f0, L_000001f7f2c1cb30; +L_000001f7f2c1cdb0 .part/v L_000001f7f2c1ee20, L_000001f7f2c1ddf0, 1; +S_000001f7f2c11bd0 .scope module, "data_reg[7]_i_6" "LUT2" 3 169, 9 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I0"; + .port_info 1 /INPUT 1 "I1"; + .port_info 2 /OUTPUT 1 "O"; +P_000001f7f2b92d60 .param/l "INIT" 0 9 15, C4<0110>; +v000001f7f2c0ab70_0 .net "I0", 0 0, L_000001f7f2c1d030; 1 drivers +v000001f7f2c0a850_0 .net "I1", 0 0, L_000001f7f2c1c950; 1 drivers +v000001f7f2c0a8f0_0 .net "O", 0 0, L_000001f7f2c1c810; alias, 1 drivers +L_000001f7f2c1ee68 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>; +v000001f7f2c0acb0_0 .net/2u *"_ivl_2", 3 0, L_000001f7f2c1ee68; 1 drivers +v000001f7f2c0b570_0 .net "_w_idx", 1 0, L_000001f7f2c1d710; 1 drivers +L_000001f7f2c1d710 .concat [ 1 1 0 0], L_000001f7f2c1d030, L_000001f7f2c1c950; +L_000001f7f2c1c810 .part/v L_000001f7f2c1ee68, L_000001f7f2c1d710, 1; +S_000001f7f2c11590 .scope module, "data_reg_reg[0]" "FDCE" 3 175, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2ba38b0 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2ba38e8 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2ba3920 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2ba3958 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1eeb0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66b80 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1eeb0, C4<0>, C4<0>; +L_000001f7f2c1eef8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66d40 .functor XOR 1, L_000001f7f2c1ce50, L_000001f7f2c1eef8, C4<0>, C4<0>; +v000001f7f2c0adf0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c0b430_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c0afd0_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c0b070_0 .net "D", 0 0, L_000001f7f2c1ce50; 1 drivers +v000001f7f2c0b4d0_0 .net "Q", 0 0, v000001f7f2c13320_0; 1 drivers +v000001f7f2c13be0_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1eeb0; 1 drivers +v000001f7f2c133c0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1eef8; 1 drivers +v000001f7f2c13320_0 .var "_r_Q", 0 0; +v000001f7f2c12100_0 .net "_w_CLR", 0 0, L_000001f7f2c66b80; 1 drivers +v000001f7f2c13280_0 .net "_w_D", 0 0, L_000001f7f2c66d40; 1 drivers +S_000001f7f2c10140 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c11590; + .timescale -12 -12; +E_000001f7f2b92de0 .event posedge, v000001f7f2c12100_0, v000001f7f2b9a180_0; +S_000001f7f2c10780 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c11590; + .timescale -12 -12; +S_000001f7f2c11270 .scope module, "data_reg_reg[1]" "FDCE" 3 183, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2b131d0 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2b13208 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2b13240 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2b13278 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1ef40 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66410 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1ef40, C4<0>, C4<0>; +L_000001f7f2c1ef88 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66480 .functor XOR 1, L_000001f7f2c1ca90, L_000001f7f2c1ef88, C4<0>, C4<0>; +v000001f7f2c121a0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c12240_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c13d20_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c12740_0 .net "D", 0 0, L_000001f7f2c1ca90; 1 drivers +v000001f7f2c131e0_0 .net "Q", 0 0, v000001f7f2c13b40_0; 1 drivers +v000001f7f2c12f60_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1ef40; 1 drivers +v000001f7f2c13780_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1ef88; 1 drivers +v000001f7f2c13b40_0 .var "_r_Q", 0 0; +v000001f7f2c13dc0_0 .net "_w_CLR", 0 0, L_000001f7f2c66410; 1 drivers +v000001f7f2c13000_0 .net "_w_D", 0 0, L_000001f7f2c66480; 1 drivers +S_000001f7f2c10c30 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c11270; + .timescale -12 -12; +E_000001f7f2b92ee0 .event posedge, v000001f7f2c13dc0_0, v000001f7f2b9a180_0; +S_000001f7f2c11720 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c11270; + .timescale -12 -12; +S_000001f7f2c10f50 .scope module, "data_reg_reg[2]" "FDCE" 3 191, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2b13700 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2b13738 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2b13770 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2b137a8 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1efd0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66560 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1efd0, C4<0>, C4<0>; +L_000001f7f2c1f018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66250 .functor XOR 1, L_000001f7f2c1d7b0, L_000001f7f2c1f018, C4<0>, C4<0>; +v000001f7f2c138c0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c12d80_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c12e20_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c12ec0_0 .net "D", 0 0, L_000001f7f2c1d7b0; 1 drivers +v000001f7f2c13e60_0 .net "Q", 0 0, v000001f7f2c12ba0_0; 1 drivers +v000001f7f2c13c80_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1efd0; 1 drivers +v000001f7f2c12a60_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f018; 1 drivers +v000001f7f2c12ba0_0 .var "_r_Q", 0 0; +v000001f7f2c13960_0 .net "_w_CLR", 0 0, L_000001f7f2c66560; 1 drivers +v000001f7f2c13a00_0 .net "_w_D", 0 0, L_000001f7f2c66250; 1 drivers +S_000001f7f2c102d0 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c10f50; + .timescale -12 -12; +E_000001f7f2b930e0 .event posedge, v000001f7f2c13960_0, v000001f7f2b9a180_0; +S_000001f7f2c10aa0 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c10f50; + .timescale -12 -12; +S_000001f7f2c10910 .scope module, "data_reg_reg[3]" "FDCE" 3 199, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2b14040 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2b14078 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2b140b0 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2b140e8 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1f060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66c60 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f060, C4<0>, C4<0>; +L_000001f7f2c1f0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66aa0 .functor XOR 1, L_000001f7f2c1cbd0, L_000001f7f2c1f0a8, C4<0>, C4<0>; +v000001f7f2c11fc0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c12060_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c122e0_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c12380_0 .net "D", 0 0, L_000001f7f2c1cbd0; 1 drivers +v000001f7f2c12420_0 .net "Q", 0 0, v000001f7f2c129c0_0; 1 drivers +v000001f7f2c130a0_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f060; 1 drivers +v000001f7f2c136e0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f0a8; 1 drivers +v000001f7f2c129c0_0 .var "_r_Q", 0 0; +v000001f7f2c12c40_0 .net "_w_CLR", 0 0, L_000001f7f2c66c60; 1 drivers +v000001f7f2c124c0_0 .net "_w_D", 0 0, L_000001f7f2c66aa0; 1 drivers +S_000001f7f2c11a40 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c10910; + .timescale -12 -12; +E_000001f7f2b94020 .event posedge, v000001f7f2c12c40_0, v000001f7f2b9a180_0; +S_000001f7f2c10dc0 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c10910; + .timescale -12 -12; +S_000001f7f2c105f0 .scope module, "data_reg_reg[3]_i_1" "CARRY4" 3 206, 12 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "CI"; + .port_info 1 /INPUT 1 "CYINIT"; + .port_info 2 /INPUT 4 "DI"; + .port_info 3 /INPUT 4 "S"; + .port_info 4 /OUTPUT 4 "CO"; + .port_info 5 /OUTPUT 4 "O"; +L_000001f7f2c665d0 .functor OR 1, L_000001f7f2c1eb98, L_000001f7f2c1eb98, C4<0>, C4<0>; +L_000001f7f2c66640 .functor OR 1, L_000001f7f2c1eb98, L_000001f7f2c1eb98, C4<0>, C4<0>; +L_000001f7f2c666b0 .functor XOR 4, L_000001f7f2c6a100, L_000001f7f2c6a060, C4<0000>, C4<0000>; +v000001f7f2c12560_0 .net "CI", 0 0, L_000001f7f2c1eb98; alias, 1 drivers +v000001f7f2c13140_0 .net "CO", 3 0, L_000001f7f2c6a4c0; 1 drivers +v000001f7f2c12600_0 .net "CYINIT", 0 0, L_000001f7f2c1eb98; alias, 1 drivers +v000001f7f2c126a0_0 .net "DI", 3 0, L_000001f7f2c698e0; 1 drivers +v000001f7f2c13460_0 .net "O", 3 0, L_000001f7f2c666b0; 1 drivers +v000001f7f2c13820_0 .net "S", 3 0, L_000001f7f2c6a100; 1 drivers +v000001f7f2c127e0_0 .net *"_ivl_1", 0 0, L_000001f7f2c1cd10; 1 drivers +v000001f7f2c135a0_0 .net *"_ivl_11", 0 0, L_000001f7f2c1d3f0; 1 drivers +v000001f7f2c13500_0 .net *"_ivl_15", 0 0, L_000001f7f2c1d490; 1 drivers +v000001f7f2c12880_0 .net *"_ivl_17", 0 0, L_000001f7f2c1da30; 1 drivers +v000001f7f2c13aa0_0 .net *"_ivl_2", 0 0, L_000001f7f2c665d0; 1 drivers +v000001f7f2c13640_0 .net *"_ivl_21", 0 0, L_000001f7f2c1db70; 1 drivers +v000001f7f2c12b00_0 .net *"_ivl_23", 0 0, L_000001f7f2c69ca0; 1 drivers +v000001f7f2c12920_0 .net *"_ivl_28", 0 0, L_000001f7f2c66640; 1 drivers +v000001f7f2c12ce0_0 .net *"_ivl_30", 3 0, L_000001f7f2c6a060; 1 drivers +v000001f7f2c15650_0 .net *"_ivl_5", 0 0, L_000001f7f2c1cef0; 1 drivers +v000001f7f2c14750_0 .net *"_ivl_9", 0 0, L_000001f7f2c1d350; 1 drivers +v000001f7f2c15d30_0 .net "_w_CO0", 0 0, L_000001f7f2c1cf90; 1 drivers +v000001f7f2c15970_0 .net "_w_CO1", 0 0, L_000001f7f2c1d990; 1 drivers +v000001f7f2c15790_0 .net "_w_CO2", 0 0, L_000001f7f2c1dad0; 1 drivers +v000001f7f2c151f0_0 .net "_w_CO3", 0 0, L_000001f7f2c6ace0; 1 drivers +L_000001f7f2c1cd10 .part L_000001f7f2c6a100, 0, 1; +L_000001f7f2c1cef0 .part L_000001f7f2c698e0, 0, 1; +L_000001f7f2c1cf90 .functor MUXZ 1, L_000001f7f2c1cef0, L_000001f7f2c665d0, L_000001f7f2c1cd10, C4<>; +L_000001f7f2c1d350 .part L_000001f7f2c6a100, 1, 1; +L_000001f7f2c1d3f0 .part L_000001f7f2c698e0, 1, 1; +L_000001f7f2c1d990 .functor MUXZ 1, L_000001f7f2c1d3f0, L_000001f7f2c1cf90, L_000001f7f2c1d350, C4<>; +L_000001f7f2c1d490 .part L_000001f7f2c6a100, 2, 1; +L_000001f7f2c1da30 .part L_000001f7f2c698e0, 2, 1; +L_000001f7f2c1dad0 .functor MUXZ 1, L_000001f7f2c1da30, L_000001f7f2c1d990, L_000001f7f2c1d490, C4<>; +L_000001f7f2c1db70 .part L_000001f7f2c6a100, 3, 1; +L_000001f7f2c69ca0 .part L_000001f7f2c698e0, 3, 1; +L_000001f7f2c6ace0 .functor MUXZ 1, L_000001f7f2c69ca0, L_000001f7f2c1dad0, L_000001f7f2c1db70, C4<>; +L_000001f7f2c6a4c0 .concat [ 1 1 1 1], L_000001f7f2c1cf90, L_000001f7f2c1d990, L_000001f7f2c1dad0, L_000001f7f2c6ace0; +L_000001f7f2c6a060 .concat [ 1 1 1 1], L_000001f7f2c66640, L_000001f7f2c1cf90, L_000001f7f2c1d990, L_000001f7f2c1dad0; +S_000001f7f2c11d60 .scope module, "data_reg_reg[4]" "FDCE" 3 215, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2b194f0 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2b19528 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2b19560 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2b19598 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1f0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66720 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f0f0, C4<0>, C4<0>; +L_000001f7f2c1f138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66e20 .functor XOR 1, L_000001f7f2c69fc0, L_000001f7f2c1f138, C4<0>, C4<0>; +v000001f7f2c15dd0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c156f0_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c15290_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c15bf0_0 .net "D", 0 0, L_000001f7f2c69fc0; 1 drivers +v000001f7f2c14110_0 .net "Q", 0 0, v000001f7f2c15b50_0; 1 drivers +v000001f7f2c14930_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f0f0; 1 drivers +v000001f7f2c14cf0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f138; 1 drivers +v000001f7f2c15b50_0 .var "_r_Q", 0 0; +v000001f7f2c15830_0 .net "_w_CLR", 0 0, L_000001f7f2c66720; 1 drivers +v000001f7f2c13fd0_0 .net "_w_D", 0 0, L_000001f7f2c66e20; 1 drivers +S_000001f7f2c16ad0 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c11d60; + .timescale -12 -12; +E_000001f7f2b93ea0 .event posedge, v000001f7f2c15830_0, v000001f7f2b9a180_0; +S_000001f7f2c16940 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c11d60; + .timescale -12 -12; +S_000001f7f2c16c60 .scope module, "data_reg_reg[5]" "FDCE" 3 223, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2b1a980 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2b1a9b8 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2b1a9f0 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2b1aa28 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1f180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66db0 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f180, C4<0>, C4<0>; +L_000001f7f2c1f1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c669c0 .functor XOR 1, L_000001f7f2c69980, L_000001f7f2c1f1c8, C4<0>, C4<0>; +v000001f7f2c15a10_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c15ab0_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c153d0_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c15e70_0 .net "D", 0 0, L_000001f7f2c69980; 1 drivers +v000001f7f2c146b0_0 .net "Q", 0 0, v000001f7f2c14250_0; 1 drivers +v000001f7f2c141b0_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f180; 1 drivers +v000001f7f2c15c90_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f1c8; 1 drivers +v000001f7f2c14250_0 .var "_r_Q", 0 0; +v000001f7f2c142f0_0 .net "_w_CLR", 0 0, L_000001f7f2c66db0; 1 drivers +v000001f7f2c155b0_0 .net "_w_D", 0 0, L_000001f7f2c669c0; 1 drivers +S_000001f7f2c16490 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c16c60; + .timescale -12 -12; +E_000001f7f2b943e0 .event posedge, v000001f7f2c142f0_0, v000001f7f2b9a180_0; +S_000001f7f2c16300 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c16c60; + .timescale -12 -12; +S_000001f7f2c17430 .scope module, "data_reg_reg[6]" "FDCE" 3 231, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2b20730 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2b20768 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2b207a0 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2b207d8 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1f210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c668e0 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f210, C4<0>, C4<0>; +L_000001f7f2c1f258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66090 .functor XOR 1, L_000001f7f2c6a740, L_000001f7f2c1f258, C4<0>, C4<0>; +v000001f7f2c149d0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c158d0_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c14390_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c14c50_0 .net "D", 0 0, L_000001f7f2c6a740; 1 drivers +v000001f7f2c15330_0 .net "Q", 0 0, v000001f7f2c14430_0; 1 drivers +v000001f7f2c14070_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f210; 1 drivers +v000001f7f2c14ed0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f258; 1 drivers +v000001f7f2c14430_0 .var "_r_Q", 0 0; +v000001f7f2c15470_0 .net "_w_CLR", 0 0, L_000001f7f2c668e0; 1 drivers +v000001f7f2c147f0_0 .net "_w_D", 0 0, L_000001f7f2c66090; 1 drivers +S_000001f7f2c17d90 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c17430; + .timescale -12 -12; +E_000001f7f2b93da0 .event posedge, v000001f7f2c15470_0, v000001f7f2b9a180_0; +S_000001f7f2c178e0 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c17430; + .timescale -12 -12; +S_000001f7f2c175c0 .scope module, "data_reg_reg[7]" "FDCE" 3 239, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2b21bc0 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2b21bf8 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2b21c30 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2b21c68 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1f2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66bf0 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f2a0, C4<0>, C4<0>; +L_000001f7f2c1f2e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c66100 .functor XOR 1, L_000001f7f2c6a240, L_000001f7f2c1f2e8, C4<0>, C4<0>; +v000001f7f2c144d0_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c14f70_0 .net "CE", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c14570_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c14890_0 .net "D", 0 0, L_000001f7f2c6a240; 1 drivers +v000001f7f2c14a70_0 .net "Q", 0 0, v000001f7f2c15510_0; 1 drivers +v000001f7f2c14610_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f2a0; 1 drivers +v000001f7f2c14b10_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f2e8; 1 drivers +v000001f7f2c15510_0 .var "_r_Q", 0 0; +v000001f7f2c14bb0_0 .net "_w_CLR", 0 0, L_000001f7f2c66bf0; 1 drivers +v000001f7f2c14d90_0 .net "_w_D", 0 0, L_000001f7f2c66100; 1 drivers +S_000001f7f2c17a70 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c175c0; + .timescale -12 -12; +E_000001f7f2b942e0 .event posedge, v000001f7f2c14bb0_0, v000001f7f2b9a180_0; +S_000001f7f2c17c00 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c175c0; + .timescale -12 -12; +S_000001f7f2c172a0 .scope module, "data_reg_reg[7]_i_1" "CARRY4" 3 246, 12 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "CI"; + .port_info 1 /INPUT 1 "CYINIT"; + .port_info 2 /INPUT 4 "DI"; + .port_info 3 /INPUT 4 "S"; + .port_info 4 /OUTPUT 4 "CO"; + .port_info 5 /OUTPUT 4 "O"; +L_000001f7f2c661e0 .functor OR 1, L_000001f7f2c69c00, L_000001f7f2c1eb98, C4<0>, C4<0>; +L_000001f7f2c6fd70 .functor OR 1, L_000001f7f2c69c00, L_000001f7f2c1eb98, C4<0>, C4<0>; +L_000001f7f2c6fde0 .functor XOR 4, L_000001f7f2c677c0, L_000001f7f2c69d40, C4<0000>, C4<0000>; +v000001f7f2c14e30_0 .net "CI", 0 0, L_000001f7f2c69c00; alias, 1 drivers +v000001f7f2c15010_0 .net "CO", 3 0, L_000001f7f2c6aa60; 1 drivers +v000001f7f2c150b0_0 .net "CYINIT", 0 0, L_000001f7f2c1eb98; alias, 1 drivers +v000001f7f2c15150_0 .net "DI", 3 0, L_000001f7f2c6aba0; 1 drivers +v000001f7f2c198f0_0 .net "O", 3 0, L_000001f7f2c6fde0; 1 drivers +v000001f7f2c189f0_0 .net "S", 3 0, L_000001f7f2c677c0; 1 drivers +v000001f7f2c19e90_0 .net *"_ivl_1", 0 0, L_000001f7f2c6a560; 1 drivers +v000001f7f2c17ff0_0 .net *"_ivl_11", 0 0, L_000001f7f2c6a420; 1 drivers +v000001f7f2c19cb0_0 .net *"_ivl_15", 0 0, L_000001f7f2c69e80; 1 drivers +v000001f7f2c19710_0 .net *"_ivl_17", 0 0, L_000001f7f2c6ab00; 1 drivers +v000001f7f2c19d50_0 .net *"_ivl_2", 0 0, L_000001f7f2c661e0; 1 drivers +v000001f7f2c19b70_0 .net *"_ivl_21", 0 0, L_000001f7f2c6a6a0; 1 drivers +v000001f7f2c18810_0 .net *"_ivl_23", 0 0, L_000001f7f2c69b60; 1 drivers +v000001f7f2c19990_0 .net *"_ivl_28", 0 0, L_000001f7f2c6fd70; 1 drivers +v000001f7f2c18590_0 .net *"_ivl_30", 3 0, L_000001f7f2c69d40; 1 drivers +v000001f7f2c18c70_0 .net *"_ivl_5", 0 0, L_000001f7f2c6a1a0; 1 drivers +v000001f7f2c186d0_0 .net *"_ivl_9", 0 0, L_000001f7f2c6a920; 1 drivers +v000001f7f2c188b0_0 .net "_w_CO0", 0 0, L_000001f7f2c69de0; 1 drivers +v000001f7f2c19350_0 .net "_w_CO1", 0 0, L_000001f7f2c6a600; 1 drivers +v000001f7f2c18a90_0 .net "_w_CO2", 0 0, L_000001f7f2c6aec0; 1 drivers +v000001f7f2c18950_0 .net "_w_CO3", 0 0, L_000001f7f2c6a7e0; 1 drivers +L_000001f7f2c6a560 .part L_000001f7f2c677c0, 0, 1; +L_000001f7f2c6a1a0 .part L_000001f7f2c6aba0, 0, 1; +L_000001f7f2c69de0 .functor MUXZ 1, L_000001f7f2c6a1a0, L_000001f7f2c661e0, L_000001f7f2c6a560, C4<>; +L_000001f7f2c6a920 .part L_000001f7f2c677c0, 1, 1; +L_000001f7f2c6a420 .part L_000001f7f2c6aba0, 1, 1; +L_000001f7f2c6a600 .functor MUXZ 1, L_000001f7f2c6a420, L_000001f7f2c69de0, L_000001f7f2c6a920, C4<>; +L_000001f7f2c69e80 .part L_000001f7f2c677c0, 2, 1; +L_000001f7f2c6ab00 .part L_000001f7f2c6aba0, 2, 1; +L_000001f7f2c6aec0 .functor MUXZ 1, L_000001f7f2c6ab00, L_000001f7f2c6a600, L_000001f7f2c69e80, C4<>; +L_000001f7f2c6a6a0 .part L_000001f7f2c677c0, 3, 1; +L_000001f7f2c69b60 .part L_000001f7f2c6aba0, 3, 1; +L_000001f7f2c6a7e0 .functor MUXZ 1, L_000001f7f2c69b60, L_000001f7f2c6aec0, L_000001f7f2c6a6a0, C4<>; +L_000001f7f2c6aa60 .concat [ 1 1 1 1], L_000001f7f2c69de0, L_000001f7f2c6a600, L_000001f7f2c6aec0, L_000001f7f2c6a7e0; +L_000001f7f2c69d40 .concat [ 1 1 1 1], L_000001f7f2c6fd70, L_000001f7f2c69de0, L_000001f7f2c6a600, L_000001f7f2c6aec0; +S_000001f7f2c16620 .scope module, "rst_n_IBUF_inst" "IBUF" 3 253, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c6f440 .functor BUFZ 1, v000001f7f2c1c450_0, C4<0>, C4<0>, C4<0>; +v000001f7f2c18090_0 .net "I", 0 0, v000001f7f2c1c450_0; alias, 1 drivers +v000001f7f2c18310_0 .net "O", 0 0, L_000001f7f2c6f440; alias, 1 drivers +S_000001f7f2c16df0 .scope module, "valid_in_IBUF_inst" "IBUF" 3 256, 7 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c6fb40 .functor BUFZ 1, v000001f7f2c1b5f0_0, C4<0>, C4<0>, C4<0>; +v000001f7f2c19df0_0 .net "I", 0 0, v000001f7f2c1b5f0_0; alias, 1 drivers +v000001f7f2c19530_0 .net "O", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +S_000001f7f2c16f80 .scope module, "valid_out_OBUF_inst" "OBUF" 3 259, 8 1 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "I"; + .port_info 1 /OUTPUT 1 "O"; +L_000001f7f2c6f520 .functor BUFZ 1, v000001f7f2c183b0_0, C4<0>, C4<0>, C4<0>; +v000001f7f2c18770_0 .net "I", 0 0, v000001f7f2c183b0_0; alias, 1 drivers +v000001f7f2c18130_0 .net "O", 0 0, L_000001f7f2c6f520; alias, 1 drivers +S_000001f7f2c15fe0 .scope module, "valid_out_reg" "FDCE" 3 264, 11 13 0, S_000001f7f2ba6300; + .timescale -12 -12; + .port_info 0 /INPUT 1 "C"; + .port_info 1 /INPUT 1 "CE"; + .port_info 2 /INPUT 1 "CLR"; + .port_info 3 /INPUT 1 "D"; + .port_info 4 /OUTPUT 1 "Q"; +P_000001f7f2ba29c0 .param/l "INIT" 0 11 18, C4<0>; +P_000001f7f2ba29f8 .param/l "IS_CLR_INVERTED" 0 11 17, C4<0>; +P_000001f7f2ba2a30 .param/l "IS_C_INVERTED" 0 11 15, C4<0>; +P_000001f7f2ba2a68 .param/l "IS_D_INVERTED" 0 11 16, C4<0>; +L_000001f7f2c1f330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c6ff30 .functor XOR 1, L_000001f7f2c1c9f0, L_000001f7f2c1f330, C4<0>, C4<0>; +L_000001f7f2c1f378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_000001f7f2c6f2f0 .functor XOR 1, L_000001f7f2c6fb40, L_000001f7f2c1f378, C4<0>, C4<0>; +v000001f7f2c18450_0 .net "C", 0 0, L_000001f7f2b864a0; alias, 1 drivers +v000001f7f2c181d0_0 .net "CE", 0 0, L_000001f7f2c1ebe0; alias, 1 drivers +v000001f7f2c18b30_0 .net "CLR", 0 0, L_000001f7f2c1c9f0; alias, 1 drivers +v000001f7f2c18270_0 .net "D", 0 0, L_000001f7f2c6fb40; alias, 1 drivers +v000001f7f2c195d0_0 .net "Q", 0 0, v000001f7f2c183b0_0; alias, 1 drivers +v000001f7f2c19670_0 .net/2u *"_ivl_0", 0 0, L_000001f7f2c1f330; 1 drivers +v000001f7f2c18bd0_0 .net/2u *"_ivl_4", 0 0, L_000001f7f2c1f378; 1 drivers +v000001f7f2c183b0_0 .var "_r_Q", 0 0; +v000001f7f2c184f0_0 .net "_w_CLR", 0 0, L_000001f7f2c6ff30; 1 drivers +v000001f7f2c197b0_0 .net "_w_D", 0 0, L_000001f7f2c6f2f0; 1 drivers +S_000001f7f2c167b0 .scope generate, "GEN_CLK_POS" "GEN_CLK_POS" 11 42, 11 42 0, S_000001f7f2c15fe0; + .timescale -12 -12; +E_000001f7f2b93f60 .event posedge, v000001f7f2c184f0_0, v000001f7f2b9a180_0; +S_000001f7f2c16170 .scope begin, "INIT_STATE" "INIT_STATE" 11 37, 11 37 0, S_000001f7f2c15fe0; + .timescale -12 -12; + .scope S_000001f7f2c10140; +T_0 ; + %wait E_000001f7f2b92de0; + %load/vec4 v000001f7f2c12100_0; + %flag_set/vec4 8; + %jmp/0xz T_0.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c13320_0, 0; + %jmp T_0.1; +T_0.0 ; + %load/vec4 v000001f7f2c0b430_0; + %flag_set/vec4 8; + %jmp/0xz T_0.2, 8; + %load/vec4 v000001f7f2c13280_0; + %assign/vec4 v000001f7f2c13320_0, 0; +T_0.2 ; +T_0.1 ; + %jmp T_0; + .thread T_0; + .scope S_000001f7f2c11590; +T_1 ; + %fork t_1, S_000001f7f2c10780; + %jmp t_0; + .scope S_000001f7f2c10780; +t_1 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c13320_0, 0, 1; + %end; + .scope S_000001f7f2c11590; +t_0 %join; + %end; + .thread T_1; + .scope S_000001f7f2c10c30; +T_2 ; + %wait E_000001f7f2b92ee0; + %load/vec4 v000001f7f2c13dc0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c13b40_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v000001f7f2c12240_0; + %flag_set/vec4 8; + %jmp/0xz T_2.2, 8; + %load/vec4 v000001f7f2c13000_0; + %assign/vec4 v000001f7f2c13b40_0, 0; +T_2.2 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_000001f7f2c11270; +T_3 ; + %fork t_3, S_000001f7f2c11720; + %jmp t_2; + .scope S_000001f7f2c11720; +t_3 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c13b40_0, 0, 1; + %end; + .scope S_000001f7f2c11270; +t_2 %join; + %end; + .thread T_3; + .scope S_000001f7f2c102d0; +T_4 ; + %wait E_000001f7f2b930e0; + %load/vec4 v000001f7f2c13960_0; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c12ba0_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v000001f7f2c12d80_0; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %load/vec4 v000001f7f2c13a00_0; + %assign/vec4 v000001f7f2c12ba0_0, 0; +T_4.2 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_000001f7f2c10f50; +T_5 ; + %fork t_5, S_000001f7f2c10aa0; + %jmp t_4; + .scope S_000001f7f2c10aa0; +t_5 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c12ba0_0, 0, 1; + %end; + .scope S_000001f7f2c10f50; +t_4 %join; + %end; + .thread T_5; + .scope S_000001f7f2c11a40; +T_6 ; + %wait E_000001f7f2b94020; + %load/vec4 v000001f7f2c12c40_0; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c129c0_0, 0; + %jmp T_6.1; +T_6.0 ; + %load/vec4 v000001f7f2c12060_0; + %flag_set/vec4 8; + %jmp/0xz T_6.2, 8; + %load/vec4 v000001f7f2c124c0_0; + %assign/vec4 v000001f7f2c129c0_0, 0; +T_6.2 ; +T_6.1 ; + %jmp T_6; + .thread T_6; + .scope S_000001f7f2c10910; +T_7 ; + %fork t_7, S_000001f7f2c10dc0; + %jmp t_6; + .scope S_000001f7f2c10dc0; +t_7 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c129c0_0, 0, 1; + %end; + .scope S_000001f7f2c10910; +t_6 %join; + %end; + .thread T_7; + .scope S_000001f7f2c16ad0; +T_8 ; + %wait E_000001f7f2b93ea0; + %load/vec4 v000001f7f2c15830_0; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c15b50_0, 0; + %jmp T_8.1; +T_8.0 ; + %load/vec4 v000001f7f2c156f0_0; + %flag_set/vec4 8; + %jmp/0xz T_8.2, 8; + %load/vec4 v000001f7f2c13fd0_0; + %assign/vec4 v000001f7f2c15b50_0, 0; +T_8.2 ; +T_8.1 ; + %jmp T_8; + .thread T_8; + .scope S_000001f7f2c11d60; +T_9 ; + %fork t_9, S_000001f7f2c16940; + %jmp t_8; + .scope S_000001f7f2c16940; +t_9 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c15b50_0, 0, 1; + %end; + .scope S_000001f7f2c11d60; +t_8 %join; + %end; + .thread T_9; + .scope S_000001f7f2c16490; +T_10 ; + %wait E_000001f7f2b943e0; + %load/vec4 v000001f7f2c142f0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c14250_0, 0; + %jmp T_10.1; +T_10.0 ; + %load/vec4 v000001f7f2c15ab0_0; + %flag_set/vec4 8; + %jmp/0xz T_10.2, 8; + %load/vec4 v000001f7f2c155b0_0; + %assign/vec4 v000001f7f2c14250_0, 0; +T_10.2 ; +T_10.1 ; + %jmp T_10; + .thread T_10; + .scope S_000001f7f2c16c60; +T_11 ; + %fork t_11, S_000001f7f2c16300; + %jmp t_10; + .scope S_000001f7f2c16300; +t_11 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c14250_0, 0, 1; + %end; + .scope S_000001f7f2c16c60; +t_10 %join; + %end; + .thread T_11; + .scope S_000001f7f2c17d90; +T_12 ; + %wait E_000001f7f2b93da0; + %load/vec4 v000001f7f2c15470_0; + %flag_set/vec4 8; + %jmp/0xz T_12.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c14430_0, 0; + %jmp T_12.1; +T_12.0 ; + %load/vec4 v000001f7f2c158d0_0; + %flag_set/vec4 8; + %jmp/0xz T_12.2, 8; + %load/vec4 v000001f7f2c147f0_0; + %assign/vec4 v000001f7f2c14430_0, 0; +T_12.2 ; +T_12.1 ; + %jmp T_12; + .thread T_12; + .scope S_000001f7f2c17430; +T_13 ; + %fork t_13, S_000001f7f2c178e0; + %jmp t_12; + .scope S_000001f7f2c178e0; +t_13 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c14430_0, 0, 1; + %end; + .scope S_000001f7f2c17430; +t_12 %join; + %end; + .thread T_13; + .scope S_000001f7f2c17a70; +T_14 ; + %wait E_000001f7f2b942e0; + %load/vec4 v000001f7f2c14bb0_0; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c15510_0, 0; + %jmp T_14.1; +T_14.0 ; + %load/vec4 v000001f7f2c14f70_0; + %flag_set/vec4 8; + %jmp/0xz T_14.2, 8; + %load/vec4 v000001f7f2c14d90_0; + %assign/vec4 v000001f7f2c15510_0, 0; +T_14.2 ; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_000001f7f2c175c0; +T_15 ; + %fork t_15, S_000001f7f2c17c00; + %jmp t_14; + .scope S_000001f7f2c17c00; +t_15 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c15510_0, 0, 1; + %end; + .scope S_000001f7f2c175c0; +t_14 %join; + %end; + .thread T_15; + .scope S_000001f7f2c167b0; +T_16 ; + %wait E_000001f7f2b93f60; + %load/vec4 v000001f7f2c184f0_0; + %flag_set/vec4 8; + %jmp/0xz T_16.0, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c183b0_0, 0; + %jmp T_16.1; +T_16.0 ; + %load/vec4 v000001f7f2c181d0_0; + %flag_set/vec4 8; + %jmp/0xz T_16.2, 8; + %load/vec4 v000001f7f2c197b0_0; + %assign/vec4 v000001f7f2c183b0_0, 0; +T_16.2 ; +T_16.1 ; + %jmp T_16; + .thread T_16; + .scope S_000001f7f2c15fe0; +T_17 ; + %fork t_17, S_000001f7f2c16170; + %jmp t_16; + .scope S_000001f7f2c16170; +t_17 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c183b0_0, 0, 1; + %end; + .scope S_000001f7f2c15fe0; +t_16 %join; + %end; + .thread T_17; + .scope S_000001f7f2b9eb50; +T_18 ; + %vpi_call 2 37 "$dumpfile", "EzLogic_tb.vcd" {0 0 0}; + %vpi_call 2 38 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001f7f2b9eb50 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c1aa10_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c1c450_0, 0, 1; + %pushi/vec4 0, 0, 8; + %store/vec4 v000001f7f2c1c630_0, 0, 8; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c1b5f0_0, 0, 1; + %pushi/vec4 0, 0, 7; + %store/vec4 v000001f7f2c1a1f0_0, 0, 7; + %pushi/vec4 0, 0, 7; + %store/vec4 v000001f7f2c1bc30_0, 0, 7; + %pushi/vec4 0, 0, 1; + %store/vec4 v000001f7f2c1b7d0_0, 0, 1; + %pushi/vec4 0, 0, 336; + %store/vec4 v000001f7f2c1ac90_0, 0, 336; + %delay 4000000, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001f7f2c1c450_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v000001f7f2c1b7d0_0, 0, 1; + %wait E_000001f7f2b95560; + %delay 4000000, 0; + %load/vec4 v000001f7f2c1ae70_0; + %flag_set/vec4 8; + %jmp/0xz T_18.0, 8; + %vpi_call 2 53 "$display", "Great! You've found the correct flag!" {0 0 0}; + %jmp T_18.1; +T_18.0 ; + %vpi_call 2 56 "$display", "Binary Data: %b", v000001f7f2c1ac90_0 {0 0 0}; + %vpi_call 2 57 "$display", "Binary Data: %b", v000001f7f2c1b550_0 {0 0 0}; + %vpi_call 2 58 "$display", "Hexadecimal Data: %h", v000001f7f2c1ac90_0 {0 0 0}; + %vpi_call 2 59 "$display", "Haha, try again!" {0 0 0}; +T_18.1 ; + %delay 20000000, 0; + %vpi_call 2 62 "$finish" {0 0 0}; + %end; + .thread T_18; + .scope S_000001f7f2b9eb50; +T_19 ; + %wait E_000001f7f2b95b20; + %load/vec4 v000001f7f2c1b7d0_0; + %pad/u 32; + %cmpi/e 1, 0, 32; + %jmp/0xz T_19.0, 4; + %load/vec4 v000001f7f2c1a1f0_0; + %pad/u 32; + %cmpi/u 42, 0, 32; + %jmp/0xz T_19.2, 5; + %load/vec4 v000001f7f2c1a1f0_0; + %addi 1, 0, 7; + %assign/vec4 v000001f7f2c1a1f0_0, 0; + %ix/getv 4, v000001f7f2c1a1f0_0; + %load/vec4a v000001f7f2c1be10, 4; + %assign/vec4 v000001f7f2c1c630_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v000001f7f2c1b5f0_0, 0; + %jmp T_19.3; +T_19.2 ; + %pushi/vec4 0, 0, 8; + %assign/vec4 v000001f7f2c1c630_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c1b5f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v000001f7f2c1b7d0_0, 0; +T_19.3 ; +T_19.0 ; + %jmp T_19; + .thread T_19; + .scope S_000001f7f2b9eb50; +T_20 ; + %wait E_000001f7f2b95b20; + %load/vec4 v000001f7f2c1b190_0; + %flag_set/vec4 8; + %jmp/0xz T_20.0, 8; + %load/vec4 v000001f7f2c1bc30_0; + %addi 1, 0, 7; + %assign/vec4 v000001f7f2c1bc30_0, 0; + %load/vec4 v000001f7f2c1add0_0; + %ix/load 5, 0, 0; + %pushi/vec4 328, 0, 34; + %load/vec4 v000001f7f2c1bc30_0; + %pad/u 32; + %muli 8, 0, 32; + %pad/u 34; + %sub; + %ix/vec4/s 4; + %assign/vec4/off/d v000001f7f2c1ac90_0, 4, 5; +T_20.0 ; + %jmp T_20; + .thread T_20; + .scope S_000001f7f2b9eb50; +T_21 ; + %delay 1000000, 0; + %load/vec4 v000001f7f2c1aa10_0; + %inv; + %store/vec4 v000001f7f2c1aa10_0, 0, 1; + %jmp T_21; + .thread T_21; +# The file index is used to find the file name in the following table. +:file_names 13; + "N/A"; + ""; + "./problem/EzLogic_tb.v"; + "./problem/EzLogic_top_synth.v"; + "./behavioral models/GND.v"; + "./behavioral models/VCC.v"; + "./behavioral models/BUFG.v"; + "./behavioral models/IBUF.v"; + "./behavioral models/OBUF.v"; + "./behavioral models/LUT2.v"; + "./behavioral models/LUT1.v"; + "./behavioral models/FDCE.v"; + "./behavioral models/CARRY4.v"; diff --git a/0ctf/EzLogic/EzLogic_tb.vcd b/0ctf/EzLogic/EzLogic_tb.vcd new file mode 100644 index 0000000..bfa4237 --- /dev/null +++ b/0ctf/EzLogic/EzLogic_tb.vcd @@ -0,0 +1,1519 @@ +$date + Sat Dec 21 20:09:40 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module EzLogic_tb $end +$var wire 336 ! data_std [0:335] $end +$var wire 1 " valid_out $end +$var wire 1 # success $end +$var wire 8 $ data_out [7:0] $end +$var parameter 16 % FLAG_TO_TEST $end +$var parameter 32 & N $end +$var reg 1 ' clk $end +$var reg 7 ( counter [6:0] $end +$var reg 7 ) counter2 [6:0] $end +$var reg 8 * data_in [7:0] $end +$var reg 336 + data_out_all [0:335] $end +$var reg 1 , rst_n $end +$var reg 1 - start $end +$var reg 1 . valid_in $end +$scope begin genblk1[0] $end +$var parameter 2 / i $end +$upscope $end +$scope begin genblk1[1] $end +$var parameter 2 0 i $end +$upscope $end +$scope begin genblk1[2] $end +$var parameter 3 1 i $end +$upscope $end +$scope begin genblk1[3] $end +$var parameter 3 2 i $end +$upscope $end +$scope begin genblk1[4] $end +$var parameter 4 3 i $end +$upscope $end +$scope begin genblk1[5] $end +$var parameter 4 4 i $end +$upscope $end +$scope begin genblk1[6] $end +$var parameter 4 5 i $end +$upscope $end +$scope begin genblk1[7] $end +$var parameter 4 6 i $end +$upscope $end +$scope begin genblk1[8] $end +$var parameter 5 7 i $end +$upscope $end +$scope begin genblk1[9] $end +$var parameter 5 8 i $end +$upscope $end +$scope begin genblk1[10] $end +$var parameter 5 9 i $end +$upscope $end +$scope begin genblk1[11] $end +$var parameter 5 : i $end +$upscope $end +$scope begin genblk1[12] $end +$var parameter 5 ; i $end +$upscope $end +$scope begin genblk1[13] $end +$var parameter 5 < i $end +$upscope $end +$scope begin genblk1[14] $end +$var parameter 5 = i $end +$upscope $end +$scope begin genblk1[15] $end +$var parameter 5 > i $end +$upscope $end +$scope begin genblk1[16] $end +$var parameter 6 ? i $end +$upscope $end +$scope begin genblk1[17] $end +$var parameter 6 @ i $end +$upscope $end +$scope begin genblk1[18] $end +$var parameter 6 A i $end +$upscope $end +$scope begin genblk1[19] $end +$var parameter 6 B i $end +$upscope $end +$scope begin genblk1[20] $end +$var parameter 6 C i $end +$upscope $end +$scope begin genblk1[21] $end +$var parameter 6 D i $end +$upscope $end +$scope begin genblk1[22] $end +$var parameter 6 E i $end +$upscope $end +$scope begin genblk1[23] $end +$var parameter 6 F i $end +$upscope $end +$scope begin genblk1[24] $end +$var parameter 6 G i $end +$upscope $end +$scope begin genblk1[25] $end +$var parameter 6 H i $end +$upscope $end +$scope begin genblk1[26] $end +$var parameter 6 I i $end +$upscope $end +$scope begin genblk1[27] $end +$var parameter 6 J i $end +$upscope $end +$scope begin genblk1[28] $end +$var parameter 6 K i $end +$upscope $end +$scope begin genblk1[29] $end +$var parameter 6 L i $end +$upscope $end +$scope begin genblk1[30] $end +$var parameter 6 M i $end +$upscope $end +$scope begin genblk1[31] $end +$var parameter 6 N i $end +$upscope $end +$scope begin genblk1[32] $end +$var parameter 7 O i $end +$upscope $end +$scope begin genblk1[33] $end +$var parameter 7 P i $end +$upscope $end +$scope begin genblk1[34] $end +$var parameter 7 Q i $end +$upscope $end +$scope begin genblk1[35] $end +$var parameter 7 R i $end +$upscope $end +$scope begin genblk1[36] $end +$var parameter 7 S i $end +$upscope $end +$scope begin genblk1[37] $end +$var parameter 7 T i $end +$upscope $end +$scope begin genblk1[38] $end +$var parameter 7 U i $end +$upscope $end +$scope begin genblk1[39] $end +$var parameter 7 V i $end +$upscope $end +$scope begin genblk1[40] $end +$var parameter 7 W i $end +$upscope $end +$scope begin genblk1[41] $end +$var parameter 7 X i $end +$upscope $end +$scope module inst $end +$var wire 1 Y \ $end +$var wire 1 Z \ $end +$var wire 1 ' clk $end +$var wire 8 [ data_in [7:0] $end +$var wire 1 , rst_n $end +$var wire 1 . valid_in $end +$var wire 1 \ valid_out_OBUF $end +$var wire 1 " valid_out $end +$var wire 1 ] valid_in_IBUF $end +$var wire 1 ^ rst_n_IBUF $end +$var wire 8 _ p_0_in [7:0] $end +$var wire 1 ` \data_reg_reg[7]_i_1_n_3 $end +$var wire 1 a \data_reg_reg[7]_i_1_n_2 $end +$var wire 1 b \data_reg_reg[7]_i_1_n_1 $end +$var wire 1 c \data_reg_reg[3]_i_1_n_3 $end +$var wire 1 d \data_reg_reg[3]_i_1_n_2 $end +$var wire 1 e \data_reg_reg[3]_i_1_n_1 $end +$var wire 1 f \data_reg_reg[3]_i_1_n_0 $end +$var wire 1 g \data_reg[7]_i_6_n_0 $end +$var wire 1 h \data_reg[7]_i_5_n_0 $end +$var wire 1 i \data_reg[7]_i_4_n_0 $end +$var wire 1 j \data_reg[7]_i_3_n_0 $end +$var wire 1 k \data_reg[7]_i_2_n_0 $end +$var wire 1 l \data_reg[3]_i_5_n_0 $end +$var wire 1 m \data_reg[3]_i_4_n_0 $end +$var wire 1 n \data_reg[3]_i_3_n_0 $end +$var wire 1 o \data_reg[3]_i_2_n_0 $end +$var wire 8 p data_out_OBUF [7:0] $end +$var wire 8 q data_out [7:0] $end +$var wire 8 r data_in_IBUF [7:0] $end +$var wire 1 s clk_IBUF_BUFG $end +$var wire 1 t clk_IBUF $end +$scope module GND $end +$var wire 1 Y G $end +$upscope $end +$scope module VCC $end +$var wire 1 Z P $end +$upscope $end +$scope module clk_IBUF_BUFG_inst $end +$var wire 1 s O $end +$var wire 1 t I $end +$upscope $end +$scope module clk_IBUF_inst $end +$var wire 1 ' I $end +$var wire 1 t O $end +$upscope $end +$scope module data_in_IBUF[0]_inst $end +$var wire 1 u I $end +$var wire 1 v O $end +$upscope $end +$scope module data_in_IBUF[1]_inst $end +$var wire 1 w I $end +$var wire 1 x O $end +$upscope $end +$scope module data_in_IBUF[2]_inst $end +$var wire 1 y I $end +$var wire 1 z O $end +$upscope $end +$scope module data_in_IBUF[3]_inst $end +$var wire 1 { I $end +$var wire 1 | O $end +$upscope $end +$scope module data_in_IBUF[4]_inst $end +$var wire 1 } I $end +$var wire 1 ~ O $end +$upscope $end +$scope module data_in_IBUF[5]_inst $end +$var wire 1 !" I $end +$var wire 1 "" O $end +$upscope $end +$scope module data_in_IBUF[6]_inst $end +$var wire 1 #" I $end +$var wire 1 $" O $end +$upscope $end +$scope module data_in_IBUF[7]_inst $end +$var wire 1 %" I $end +$var wire 1 &" O $end +$upscope $end +$scope module data_out_OBUF[0]_inst $end +$var wire 1 '" I $end +$var wire 1 (" O $end +$upscope $end +$scope module data_out_OBUF[1]_inst $end +$var wire 1 )" I $end +$var wire 1 *" O $end +$upscope $end +$scope module data_out_OBUF[2]_inst $end +$var wire 1 +" I $end +$var wire 1 ," O $end +$upscope $end +$scope module data_out_OBUF[3]_inst $end +$var wire 1 -" I $end +$var wire 1 ." O $end +$upscope $end +$scope module data_out_OBUF[4]_inst $end +$var wire 1 /" I $end +$var wire 1 0" O $end +$upscope $end +$scope module data_out_OBUF[5]_inst $end +$var wire 1 1" I $end +$var wire 1 2" O $end +$upscope $end +$scope module data_out_OBUF[6]_inst $end +$var wire 1 3" I $end +$var wire 1 4" O $end +$upscope $end +$scope module data_out_OBUF[7]_inst $end +$var wire 1 5" I $end +$var wire 1 6" O $end +$upscope $end +$scope module data_reg[3]_i_2 $end +$var wire 1 7" I0 $end +$var wire 1 8" I1 $end +$var wire 2 9" _w_idx [1:0] $end +$var wire 1 o O $end +$var parameter 4 :" INIT $end +$upscope $end +$scope module data_reg[3]_i_3 $end +$var wire 1 ;" I0 $end +$var wire 1 <" I1 $end +$var wire 2 =" _w_idx [1:0] $end +$var wire 1 n O $end +$var parameter 4 >" INIT $end +$upscope $end +$scope module data_reg[3]_i_4 $end +$var wire 1 ?" I0 $end +$var wire 1 @" I1 $end +$var wire 2 A" _w_idx [1:0] $end +$var wire 1 m O $end +$var parameter 4 B" INIT $end +$upscope $end +$scope module data_reg[3]_i_5 $end +$var wire 1 C" I0 $end +$var wire 1 D" I1 $end +$var wire 2 E" _w_idx [1:0] $end +$var wire 1 l O $end +$var parameter 4 F" INIT $end +$upscope $end +$scope module data_reg[7]_i_2 $end +$var wire 1 k O $end +$var wire 1 ^ I0 $end +$var parameter 2 G" INIT $end +$upscope $end +$scope module data_reg[7]_i_3 $end +$var wire 1 H" I0 $end +$var wire 1 I" I1 $end +$var wire 2 J" _w_idx [1:0] $end +$var wire 1 j O $end +$var parameter 4 K" INIT $end +$upscope $end +$scope module data_reg[7]_i_4 $end +$var wire 1 L" I0 $end +$var wire 1 M" I1 $end +$var wire 2 N" _w_idx [1:0] $end +$var wire 1 i O $end +$var parameter 4 O" INIT $end +$upscope $end +$scope module data_reg[7]_i_5 $end +$var wire 1 P" I0 $end +$var wire 1 Q" I1 $end +$var wire 2 R" _w_idx [1:0] $end +$var wire 1 h O $end +$var parameter 4 S" INIT $end +$upscope $end +$scope module data_reg[7]_i_6 $end +$var wire 1 T" I0 $end +$var wire 1 U" I1 $end +$var wire 2 V" _w_idx [1:0] $end +$var wire 1 g O $end +$var parameter 4 W" INIT $end +$upscope $end +$scope module data_reg_reg[0] $end +$var wire 1 s C $end +$var wire 1 k CLR $end +$var wire 1 X" D $end +$var wire 1 Y" _w_CLR $end +$var wire 1 Z" _w_D $end +$var wire 1 [" Q $end +$var wire 1 ] CE $end +$var parameter 1 \" INIT $end +$var parameter 1 ]" IS_CLR_INVERTED $end +$var parameter 1 ^" IS_C_INVERTED $end +$var parameter 1 _" IS_D_INVERTED $end +$var reg 1 [" _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$scope module data_reg_reg[1] $end +$var wire 1 s C $end +$var wire 1 k CLR $end +$var wire 1 `" D $end +$var wire 1 a" _w_CLR $end +$var wire 1 b" _w_D $end +$var wire 1 c" Q $end +$var wire 1 ] CE $end +$var parameter 1 d" INIT $end +$var parameter 1 e" IS_CLR_INVERTED $end +$var parameter 1 f" IS_C_INVERTED $end +$var parameter 1 g" IS_D_INVERTED $end +$var reg 1 c" _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$scope module data_reg_reg[2] $end +$var wire 1 s C $end +$var wire 1 k CLR $end +$var wire 1 h" D $end +$var wire 1 i" _w_CLR $end +$var wire 1 j" _w_D $end +$var wire 1 k" Q $end +$var wire 1 ] CE $end +$var parameter 1 l" INIT $end +$var parameter 1 m" IS_CLR_INVERTED $end +$var parameter 1 n" IS_C_INVERTED $end +$var parameter 1 o" IS_D_INVERTED $end +$var reg 1 k" _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$scope module data_reg_reg[3] $end +$var wire 1 s C $end +$var wire 1 k CLR $end +$var wire 1 p" D $end +$var wire 1 q" _w_CLR $end +$var wire 1 r" _w_D $end +$var wire 1 s" Q $end +$var wire 1 ] CE $end +$var parameter 1 t" INIT $end +$var parameter 1 u" IS_CLR_INVERTED $end +$var parameter 1 v" IS_C_INVERTED $end +$var parameter 1 w" IS_D_INVERTED $end +$var reg 1 s" _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$scope module data_reg_reg[3]_i_1 $end +$var wire 1 Y CI $end +$var wire 1 Y CYINIT $end +$var wire 4 x" DI [3:0] $end +$var wire 4 y" O [3:0] $end +$var wire 4 z" S [3:0] $end +$var wire 1 {" _w_CO3 $end +$var wire 1 |" _w_CO2 $end +$var wire 1 }" _w_CO1 $end +$var wire 1 ~" _w_CO0 $end +$var wire 4 !# CO [3:0] $end +$upscope $end +$scope module data_reg_reg[4] $end +$var wire 1 s C $end +$var wire 1 k CLR $end +$var wire 1 "# D $end +$var wire 1 ## _w_CLR $end +$var wire 1 $# _w_D $end +$var wire 1 %# Q $end +$var wire 1 ] CE $end +$var parameter 1 &# INIT $end +$var parameter 1 '# IS_CLR_INVERTED $end +$var parameter 1 (# IS_C_INVERTED $end +$var parameter 1 )# IS_D_INVERTED $end +$var reg 1 %# _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$scope module data_reg_reg[5] $end +$var wire 1 s C $end +$var wire 1 k CLR $end +$var wire 1 *# D $end +$var wire 1 +# _w_CLR $end +$var wire 1 ,# _w_D $end +$var wire 1 -# Q $end +$var wire 1 ] CE $end +$var parameter 1 .# INIT $end +$var parameter 1 /# IS_CLR_INVERTED $end +$var parameter 1 0# IS_C_INVERTED $end +$var parameter 1 1# IS_D_INVERTED $end +$var reg 1 -# _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$scope module data_reg_reg[6] $end +$var wire 1 s C $end +$var wire 1 k CLR $end +$var wire 1 2# D $end +$var wire 1 3# _w_CLR $end +$var wire 1 4# _w_D $end +$var wire 1 5# Q $end +$var wire 1 ] CE $end +$var parameter 1 6# INIT $end +$var parameter 1 7# IS_CLR_INVERTED $end +$var parameter 1 8# IS_C_INVERTED $end +$var parameter 1 9# IS_D_INVERTED $end +$var reg 1 5# _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$scope module data_reg_reg[7] $end +$var wire 1 s C $end +$var wire 1 k CLR $end +$var wire 1 :# D $end +$var wire 1 ;# _w_CLR $end +$var wire 1 <# _w_D $end +$var wire 1 =# Q $end +$var wire 1 ] CE $end +$var parameter 1 ># INIT $end +$var parameter 1 ?# IS_CLR_INVERTED $end +$var parameter 1 @# IS_C_INVERTED $end +$var parameter 1 A# IS_D_INVERTED $end +$var reg 1 =# _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$scope module data_reg_reg[7]_i_1 $end +$var wire 1 f CI $end +$var wire 1 Y CYINIT $end +$var wire 4 B# DI [3:0] $end +$var wire 4 C# O [3:0] $end +$var wire 4 D# S [3:0] $end +$var wire 1 E# _w_CO3 $end +$var wire 1 F# _w_CO2 $end +$var wire 1 G# _w_CO1 $end +$var wire 1 H# _w_CO0 $end +$var wire 4 I# CO [3:0] $end +$upscope $end +$scope module rst_n_IBUF_inst $end +$var wire 1 , I $end +$var wire 1 ^ O $end +$upscope $end +$scope module valid_in_IBUF_inst $end +$var wire 1 . I $end +$var wire 1 ] O $end +$upscope $end +$scope module valid_out_OBUF_inst $end +$var wire 1 " O $end +$var wire 1 \ I $end +$upscope $end +$scope module valid_out_reg $end +$var wire 1 s C $end +$var wire 1 Z CE $end +$var wire 1 k CLR $end +$var wire 1 ] D $end +$var wire 1 J# _w_CLR $end +$var wire 1 K# _w_D $end +$var wire 1 \ Q $end +$var parameter 1 L# INIT $end +$var parameter 1 M# IS_CLR_INVERTED $end +$var parameter 1 N# IS_C_INVERTED $end +$var parameter 1 O# IS_D_INVERTED $end +$var reg 1 \ _r_Q $end +$scope begin GEN_CLK_POS $end +$upscope $end +$scope begin INIT_STATE $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +$comment Show the parameter values. $end +$dumpall +0O# +0N# +0M# +0L# +0A# +0@# +0?# +0># +09# +08# +07# +06# +01# +00# +0/# +0.# +0)# +0(# +0'# +0&# +0w" +0v" +0u" +0t" +0o" +0n" +0m" +0l" +0g" +0f" +0e" +0d" +0_" +0^" +0]" +0\" +b110 W" +b110 S" +b110 O" +b110 K" +b1 G" +b110 F" +b110 B" +b110 >" +b110 :" +b101001 X +b101000 W +b100111 V +b100110 U +b100101 T +b100100 S +b100011 R +b100010 Q +b100001 P +b100000 O +b11111 N +b11110 M +b11101 L +b11100 K +b11011 J +b11010 I +b11001 H +b11000 G +b10111 F +b10110 E +b10101 D +b10100 C +b10011 B +b10010 A +b10001 @ +b10000 ? +b1111 > +b1110 = +b1101 < +b1100 ; +b1011 : +b1010 9 +b1001 8 +b1000 7 +b111 6 +b110 5 +b101 4 +b100 3 +b11 2 +b10 1 +b1 0 +b0 / +b101010 & +b110111100110000 % +$end +#0 +$dumpvars +0K# +1J# +b0 I# +0H# +0G# +0F# +0E# +b0 D# +b0 C# +b0 B# +0=# +0<# +1;# +0:# +05# +04# +13# +02# +0-# +0,# +1+# +0*# +0%# +0$# +1## +0"# +b0 !# +0~" +0}" +0|" +0{" +b0 z" +b0 y" +b0 x" +0s" +0r" +1q" +0p" +0k" +0j" +1i" +0h" +0c" +0b" +1a" +0`" +0[" +0Z" +1Y" +0X" +b0 V" +0U" +0T" +b0 R" +0Q" +0P" +b0 N" +0M" +0L" +b0 J" +0I" +0H" +b0 E" +0D" +0C" +b0 A" +0@" +0?" +b0 =" +0<" +0;" +b0 9" +08" +07" +06" +05" +04" +03" +02" +01" +00" +0/" +0." +0-" +0," +0+" +0*" +0)" +0(" +0'" +0&" +0%" +0$" +0#" +0"" +0!" +0~ +0} +0| +0{ +0z +0y +0x +0w +0v +0u +0t +0s +b0 r +b0 q +b0 p +0o +0n +0m +0l +1k +0j +0i +0h +0g +0f +0e +0d +0c +0b +0a +0` +b0 _ +0^ +0] +0\ +b0 [ +1Z +0Y +0. +0- +0, +b0 + +b0 * +b0 ) +b0 ( +0' +b0 $ +0# +0" +b1100000111100010011101010101101001001011110010111111100010001110111011001011000101110110011110000101100100000001100110010100111011011011001011001000010111110010010101001010011001100011001110000101111011011100010100001101111000100011011001010010011001010100100110100000001011010010111100111001001100001100001010100101101100011101010011 ! +$end +#1000000 +1s +1t +1' +#2000000 +0s +0t +0' +#3000000 +1s +1t +1' +#4000000 +0Y" +0a" +0i" +0q" +0## +0+# +03# +0;# +0J# +0s +0t +0' +1- +0k +1^ +1, +#5000000 +1K# +1] +1. +b1 ( +1s +1t +1' +#6000000 +0s +0t +0' +#7000000 +1" +1\ +b10 ( +1s +1t +1' +#8000000 +0s +0t +0' +#9000000 +b11 ( +b1 ) +1s +1t +1' +#10000000 +0s +0t +0' +#11000000 +b10 ) +b100 ( +1s +1t +1' +#12000000 +0s +0t +0' +#13000000 +b101 ( +b11 ) +1s +1t +1' +#14000000 +0s +0t +0' +#15000000 +b100 ) +b110 ( +1s +1t +1' +#16000000 +0s +0t +0' +#17000000 +b111 ( +b101 ) +1s +1t +1' +#18000000 +0s +0t +0' +#19000000 +b110 ) +b1000 ( +1s +1t +1' +#20000000 +0s +0t +0' +#21000000 +b1001 ( +b111 ) +1s +1t +1' +#22000000 +0s +0t +0' +#23000000 +b1000 ) +b1010 ( +1s +1t +1' +#24000000 +0s +0t +0' +#25000000 +b1011 ( +b1001 ) +1s +1t +1' +#26000000 +0s +0t +0' +#27000000 +b1010 ) +b1100 ( +1s +1t +1' +#28000000 +0s +0t +0' +#29000000 +b1101 ( +b1011 ) +1s +1t +1' +#30000000 +0s +0t +0' +#31000000 +b1100 ) +b1110 ( +1s +1t +1' +#32000000 +0s +0t +0' +#33000000 +b1111 ( +b1101 ) +1s +1t +1' +#34000000 +0s +0t +0' +#35000000 +b1110 ) +b10000 ( +1s +1t +1' +#36000000 +0s +0t +0' +#37000000 +b10001 ( +b1111 ) +1s +1t +1' +#38000000 +0s +0t +0' +#39000000 +b10000 ) +b10010 ( +1s +1t +1' +#40000000 +0s +0t +0' +#41000000 +b10011 ( +b10001 ) +1s +1t +1' +#42000000 +0s +0t +0' +#43000000 +b10010 ) +b10100 ( +1s +1t +1' +#44000000 +0s +0t +0' +#45000000 +b10101 ( +b10011 ) +1s +1t +1' +#46000000 +0s +0t +0' +#47000000 +b10100 ) +b10110 ( +1s +1t +1' +#48000000 +0s +0t +0' +#49000000 +b10111 ( +b10101 ) +1s +1t +1' +#50000000 +0s +0t +0' +#51000000 +b10110 ) +b11000 ( +1s +1t +1' +#52000000 +0s +0t +0' +#53000000 +b11001 ( +b10111 ) +1s +1t +1' +#54000000 +0s +0t +0' +#55000000 +b11000 ) +b11010 ( +1s +1t +1' +#56000000 +0s +0t +0' +#57000000 +b11011 ( +b11001 ) +1s +1t +1' +#58000000 +0s +0t +0' +#59000000 +b11010 ) +b11100 ( +1s +1t +1' +#60000000 +0s +0t +0' +#61000000 +b11101 ( +b11011 ) +1s +1t +1' +#62000000 +0s +0t +0' +#63000000 +b11100 ) +b11110 ( +1s +1t +1' +#64000000 +0s +0t +0' +#65000000 +b11111 ( +b11101 ) +1s +1t +1' +#66000000 +0s +0t +0' +#67000000 +b11110 ) +b100000 ( +1s +1t +1' +#68000000 +0s +0t +0' +#69000000 +b100001 ( +b11111 ) +1s +1t +1' +#70000000 +0s +0t +0' +#71000000 +b100000 ) +b100010 ( +1s +1t +1' +#72000000 +0s +0t +0' +#73000000 +b100011 ( +b100001 ) +1s +1t +1' +#74000000 +0s +0t +0' +#75000000 +b100010 ) +b100100 ( +1s +1t +1' +#76000000 +0s +0t +0' +#77000000 +b100101 ( +b100011 ) +1s +1t +1' +#78000000 +0s +0t +0' +#79000000 +b100100 ) +b100110 ( +1s +1t +1' +#80000000 +0s +0t +0' +#81000000 +b100111 ( +b100101 ) +1s +1t +1' +#82000000 +0s +0t +0' +#83000000 +b100110 ) +b101000 ( +1s +1t +1' +#84000000 +0s +0t +0' +#85000000 +1r" +1j" +1b" +1Z" +14# +1,# +1p" +1h" +1`" +1X" +12# +1*# +b1111 y" +b1101111 _ +b110 C# +1l +b10 E" +1D" +1m +b10 A" +1@" +1n +b10 =" +1<" +b1111 z" +1o +b10 9" +18" +1h +b10 R" +1Q" +b110 D# +1i +b10 N" +1M" +1v +1u +1x +1w +1z +1y +1| +1{ +1"" +1!" +b1101111 r +1$" +1#" +b1101111 * +b1101111 [ +b101001 ( +b100111 ) +1s +1t +1' +#86000000 +0s +0t +0' +#87000000 +1<# +1b +1:# +04# +1` +1a +02# +1,# +1F# +0Z" +1H# +1*# +b111 I# +1G# +0X" +b1010 C# +b10101110 _ +b1110 y" +0l +b0 E" +0D" +0@" +0<" +08" +1U" +0M" +1i +b1 N" +1L" +1(" +1'" +0g +b11 V" +1T" +1*" +1)" +1m +b1 A" +1?" +1," +1+" +b111 B# +b100 D# +0h +b11 R" +1P" +1." +1-" +1o +b1 9" +17" +12" +11" +b1110 x" +b1110 z" +1n +b1 =" +1;" +b1101111 $ +b1101111 q +14" +13" +0v +0u +0x +0w +0z +0y +0| +0{ +1~ +1} +b110000 r +0$" +0#" +1[" +1c" +1k" +1s" +1-# +b1101111 p +15# +b101000 ) +b110000 * +b110000 [ +b101010 ( +1s +1t +1' +#88000000 +0s +0t +0' +#89000000 +0a +0` +0b +0G# +0j" +1<# +04# +1,# +1$# +0H# +0F# +0h" +1:# +02# +1*# +1"# +b0 I# +0E# +b1010 y" +b10111010 _ +b1011 C# +1g +b1 V" +0U" +1h +b1 R" +0Q" +b11 B# +0i +b0 N" +0L" +0(" +0'" +b1010 x" +b1010 z" +0n +b0 =" +0;" +04" +03" +b1011 D# +1j +b1 J" +1H" +b10101110 $ +b10101110 q +16" +15" +0K# +0~ +0} +b0 r +0"" +0!" +0[" +05# +b10101110 p +1=# +0- +0] +0. +b0 * +b0 [ +b110111100000000 + +b101001 ) +1s +1t +1' +#90000000 +0s +0t +0' +#91000000 +0" +0\ +b110111110101110 + +b101010 ) +1s +1t +1' +#92000000 +0s +0t +0' +#93000000 +1s +1t +1' +#94000000 +0s +0t +0' +#95000000 +1s +1t +1' +#96000000 +0s +0t +0' +#97000000 +1s +1t +1' +#98000000 +0s +0t +0' +#99000000 +1s +1t +1' +#100000000 +0s +0t +0' +#101000000 +1s +1t +1' +#102000000 +0s +0t +0' +#103000000 +1s +1t +1' +#104000000 +0s +0t +0' +#105000000 +1s +1t +1' +#106000000 +0s +0t +0' +#107000000 +1s +1t +1' +#108000000 +0s +0t +0' +#109000000 +1s +1t +1' +#110000000 +0s +0t +0' +#111000000 +1s +1t +1' +#112000000 +0s +0t +0' +#113000000 +1s +1t +1' diff --git a/0ctf/EzLogic/behavioral models/BUFG.v b/0ctf/EzLogic/behavioral models/BUFG.v new file mode 100644 index 0000000..d513798 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/BUFG.v @@ -0,0 +1,22 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// BUFG primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/*verilator coverage_off*/ +module BUFG +( + input I, + output O /* verilator clocker */ +); + + assign O = I; + +endmodule +/*verilator coverage_on*/ \ No newline at end of file diff --git a/0ctf/EzLogic/behavioral models/CARRY4.v b/0ctf/EzLogic/behavioral models/CARRY4.v new file mode 100644 index 0000000..eaed87d --- /dev/null +++ b/0ctf/EzLogic/behavioral models/CARRY4.v @@ -0,0 +1,38 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// CARRY4 primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module CARRY4 +( + // Carry cascade input + input wire CI, + // + input wire CYINIT, + // Carry MUX data input + input wire [3:0] DI, + // Carry MUX select line + input wire [3:0] S, + // Carry out of each stage of the chain + output wire [3:0] CO, + // Carry chain XOR general data out + output wire [3:0] O +); + wire _w_CO0 = S[0] ? CI | CYINIT : DI[0]; + wire _w_CO1 = S[1] ? _w_CO0 : DI[1]; + wire _w_CO2 = S[2] ? _w_CO1 : DI[2]; + wire _w_CO3 = S[3] ? _w_CO2 : DI[3]; + + assign CO = { _w_CO3, _w_CO2, _w_CO1, _w_CO0 }; + + assign O = S ^ { _w_CO2, _w_CO1, _w_CO0, CI | CYINIT }; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/FDCE.v b/0ctf/EzLogic/behavioral models/FDCE.v new file mode 100644 index 0000000..fd753e4 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/FDCE.v @@ -0,0 +1,69 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// FDCE primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module FDCE +#( + parameter [0:0] IS_C_INVERTED = 1'b0, + parameter [0:0] IS_D_INVERTED = 1'b0, + parameter [0:0] IS_CLR_INVERTED = 1'b0, + parameter [0:0] INIT = 1'b0 +) +( + // Clock + input wire C, + // Clock enable + input wire CE, + // Asynchronous clear + input wire CLR, + // Data in + input wire D, + // Data out + output wire Q +); + reg _r_Q; + + wire _w_CLR = CLR ^ IS_CLR_INVERTED; + wire _w_D = D ^ IS_D_INVERTED; + + initial begin : INIT_STATE + _r_Q = INIT[0]; + end + + generate + if (IS_C_INVERTED) begin : GEN_CLK_NEG + always @(negedge C or posedge _w_CLR) begin + + if (_w_CLR) begin + _r_Q <= 1'b0; + end + else if (CE) begin + _r_Q <= _w_D; + end + end + end + else begin : GEN_CLK_POS + always @(posedge C or posedge _w_CLR) begin + + if (_w_CLR) begin + _r_Q <= 1'b0; + end + else if (CE) begin + _r_Q <= _w_D; + end + end + end + endgenerate + + assign Q = _r_Q; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/GND.v b/0ctf/EzLogic/behavioral models/GND.v new file mode 100644 index 0000000..be5f5fe --- /dev/null +++ b/0ctf/EzLogic/behavioral models/GND.v @@ -0,0 +1,21 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// GND primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module GND +( + output wire G +); + + assign G = 1'b0; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/IBUF.v b/0ctf/EzLogic/behavioral models/IBUF.v new file mode 100644 index 0000000..da99860 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/IBUF.v @@ -0,0 +1,6 @@ +module IBUF( + input wire I, + output wire O +); + assign O = I; +endmodule \ No newline at end of file diff --git a/0ctf/EzLogic/behavioral models/LUT1.v b/0ctf/EzLogic/behavioral models/LUT1.v new file mode 100644 index 0000000..e1aa379 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/LUT1.v @@ -0,0 +1,24 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// LUT1 primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module LUT1 +#( + parameter [1:0] INIT = 2'b00 +) +( + input wire I0, + output wire O +); + assign O = INIT[I0]; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/LUT2.v b/0ctf/EzLogic/behavioral models/LUT2.v new file mode 100644 index 0000000..349790d --- /dev/null +++ b/0ctf/EzLogic/behavioral models/LUT2.v @@ -0,0 +1,26 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// LUT2 primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module LUT2 +#( + parameter [3:0] INIT = 4'b0000 +) +( + input wire I0, I1, + output wire O +); + wire [1:0] _w_idx = { I1, I0 }; + + assign O = INIT[_w_idx]; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/LUT3.v b/0ctf/EzLogic/behavioral models/LUT3.v new file mode 100644 index 0000000..58ce405 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/LUT3.v @@ -0,0 +1,26 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// LUT3 primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module LUT3 +#( + parameter [7:0] INIT = 8'b00000000 +) +( + input wire I0, I1, I2, + output wire O +); + wire [2:0] _w_idx = { I2, I1, I0 }; + + assign O = INIT[_w_idx]; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/LUT4.v b/0ctf/EzLogic/behavioral models/LUT4.v new file mode 100644 index 0000000..4efb227 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/LUT4.v @@ -0,0 +1,26 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// LUT4 primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module LUT4 +#( + parameter [15:0] INIT = 16'h0000 +) +( + input wire I0, I1, I2, I3, + output wire O +); + wire [3:0] _w_idx = { I3, I2, I1, I0 }; + + assign O = INIT[_w_idx]; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/LUT5.v b/0ctf/EzLogic/behavioral models/LUT5.v new file mode 100644 index 0000000..62e2402 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/LUT5.v @@ -0,0 +1,26 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// LUT5 primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module LUT5 +#( + parameter [31:0] INIT = 32'h00000000 +) +( + input wire I0, I1, I2, I3, I4, + output wire O +); + wire [4:0] _w_idx = { I4, I3, I2, I1, I0 }; + + assign O = INIT[_w_idx]; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/LUT6.v b/0ctf/EzLogic/behavioral models/LUT6.v new file mode 100644 index 0000000..8e215a2 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/LUT6.v @@ -0,0 +1,26 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// LUT6 primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module LUT6 +#( + parameter [63:0] INIT = 64'h0000000000000000 +) +( + input wire I0, I1, I2, I3, I4, I5, + output wire O +); + wire [5:0] _w_idx = { I5, I4, I3, I2, I1, I0 }; + + assign O = INIT[_w_idx]; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/MUXF7.v b/0ctf/EzLogic/behavioral models/MUXF7.v new file mode 100644 index 0000000..b15c16c --- /dev/null +++ b/0ctf/EzLogic/behavioral models/MUXF7.v @@ -0,0 +1,17 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif + +/* verilator coverage_off */ +module MUXF7 +( + input wire I0, I1, S, + output wire O +); + wire [1:0] w_data = { I1, I0 }; + + assign O = w_data[S]; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/MUXF8.v b/0ctf/EzLogic/behavioral models/MUXF8.v new file mode 100644 index 0000000..f205c07 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/MUXF8.v @@ -0,0 +1,17 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif + +/* verilator coverage_off */ +module MUXF8 +( + input wire I0, I1, S, + output wire O +); + wire [1:0] w_data = { I1, I0 }; + + assign O = w_data[S]; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/behavioral models/OBUF.v b/0ctf/EzLogic/behavioral models/OBUF.v new file mode 100644 index 0000000..1aa7a87 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/OBUF.v @@ -0,0 +1,6 @@ +module OBUF( + input wire I, + output wire O +); + assign O = I; +endmodule \ No newline at end of file diff --git a/0ctf/EzLogic/behavioral models/VCC.v b/0ctf/EzLogic/behavioral models/VCC.v new file mode 100644 index 0000000..23d77c5 --- /dev/null +++ b/0ctf/EzLogic/behavioral models/VCC.v @@ -0,0 +1,21 @@ +`ifdef verilator3 +`else +`timescale 1 ps / 1 ps +`endif +// +// VCC primitive for Xilinx FPGAs +// Compatible with Verilator tool (www.veripool.org) +// Copyright (c) 2019-2022 Frédéric REQUIN +// License : BSD +// + +/* verilator coverage_off */ +module VCC +( + output wire P +); + + assign P = 1'b1; + +endmodule +/* verilator coverage_on */ diff --git a/0ctf/EzLogic/problem/.EzLogic_tb.v.swp b/0ctf/EzLogic/problem/.EzLogic_tb.v.swp new file mode 100644 index 0000000..61032b3 Binary files /dev/null and b/0ctf/EzLogic/problem/.EzLogic_tb.v.swp differ diff --git a/0ctf/EzLogic/problem/EzLogic_tb.v b/0ctf/EzLogic/problem/EzLogic_tb.v new file mode 100644 index 0000000..7310f22 --- /dev/null +++ b/0ctf/EzLogic/problem/EzLogic_tb.v @@ -0,0 +1,91 @@ +`timescale 1us / 100ns + +module EzLogic_tb #( + parameter FLAG_TO_TEST = "o0", + parameter N = 42 +)(); + reg clk; + reg rst_n; + reg valid_in; + reg start; + reg [7:0] data_in; + reg [6:0] counter; + reg [6:0] counter2; + wire [7:0] data_out; + wire valid_out; + reg [0:8*N-1] data_out_all; + wire success; + + wire [7:0] flag_test_arr [0:N-1]; + genvar i; + generate + for (i=0;i ), + .CO({\data_reg_reg[3]_i_1_n_0 ,\data_reg_reg[3]_i_1_n_1 ,\data_reg_reg[3]_i_1_n_2 ,\data_reg_reg[3]_i_1_n_3 }), + .CYINIT(\ ), + .DI({data_out_OBUF[5],data_out_OBUF[6],data_out_OBUF[2],data_out_OBUF[4]}), + .O(p_0_in[3:0]), + .S({\data_reg[3]_i_2_n_0 ,\data_reg[3]_i_3_n_0 ,\data_reg[3]_i_4_n_0 ,\data_reg[3]_i_5_n_0 })); + FDCE #( + .INIT(1'b0)) + \data_reg_reg[4] + (.C(clk_IBUF_BUFG), + .CE(valid_in_IBUF), + .CLR(\data_reg[7]_i_2_n_0 ), + .D(p_0_in[4]), + .Q(data_out_OBUF[4])); + FDCE #( + .INIT(1'b0)) + \data_reg_reg[5] + (.C(clk_IBUF_BUFG), + .CE(valid_in_IBUF), + .CLR(\data_reg[7]_i_2_n_0 ), + .D(p_0_in[5]), + .Q(data_out_OBUF[5])); + FDCE #( + .INIT(1'b0)) + \data_reg_reg[6] + (.C(clk_IBUF_BUFG), + .CE(valid_in_IBUF), + .CLR(\data_reg[7]_i_2_n_0 ), + .D(p_0_in[6]), + .Q(data_out_OBUF[6])); + FDCE #( + .INIT(1'b0)) + \data_reg_reg[7] + (.C(clk_IBUF_BUFG), + .CE(valid_in_IBUF), + .CLR(\data_reg[7]_i_2_n_0 ), + .D(p_0_in[7]), + .Q(data_out_OBUF[7])); + (* ADDER_THRESHOLD = "35" *) + CARRY4 \data_reg_reg[7]_i_1 + (.CI(\data_reg_reg[3]_i_1_n_0 ), + .CO({\data_reg_reg[7]_i_1_n_1 ,\data_reg_reg[7]_i_1_n_2 ,\data_reg_reg[7]_i_1_n_3 }), + .CYINIT(\ ), + .DI({\ ,data_out_OBUF[0],data_out_OBUF[3],data_out_OBUF[1]}), + .O(p_0_in[7:4]), + .S({\data_reg[7]_i_3_n_0 ,\data_reg[7]_i_4_n_0 ,\data_reg[7]_i_5_n_0 ,\data_reg[7]_i_6_n_0 })); + IBUF rst_n_IBUF_inst + (.I(rst_n), + .O(rst_n_IBUF)); + IBUF valid_in_IBUF_inst + (.I(valid_in), + .O(valid_in_IBUF)); + OBUF valid_out_OBUF_inst + (.I(valid_out_OBUF), + .O(valid_out)); + FDCE #( + .INIT(1'b0)) + valid_out_reg + (.C(clk_IBUF_BUFG), + .CE(\ ), + .CLR(\data_reg[7]_i_2_n_0 ), + .D(valid_in_IBUF), + .Q(valid_out_OBUF)); +endmodule diff --git a/0ctf/EzLogic/readme.md b/0ctf/EzLogic/readme.md new file mode 100644 index 0000000..7b8e483 --- /dev/null +++ b/0ctf/EzLogic/readme.md @@ -0,0 +1,50 @@ +# EzLogic +## Problem +Our task is to reverse engineer a flag checker implemented on an **FPGA**.The hardware system is constructed from a **netlist** synthesized by Xilinx Vivado, where the netlist serves a role similar to assembly language in the software domain, representing a lower-level, more hardware-specific description. The netlist is described using **Verilog**, enabling convenient simulation of the system. + +## Knowledge +If you find yourself new to Verilog or digital integrated circuit design, that's completely fine. We're here to help with a recommended Verilog syntax tutorial and an official manual covering all the foundational components used in the netlist. + +- Verilog Syntax: https://www.chipverify.com/tutorials/verilog +- FPGA Design Elements: https://docs.amd.com/r/en-US/ug953-vivado-7series-libraries/Design-Elements + +## Simulation +For system simulation, you can choose one of the following tools: +- [Xilinx Vivado](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html) (free version is enough) +- [Icarus Verilog](https://github.com/steveicarus/iverilog) and [gtkwave](http://gtkwave.sourceforge.net/) (open-source software) + +### Using Vivado +1. Install Vivado HL WebPACK version (must select Zynq 7000 series boards support) +2. Create a project (just click "next" to the end, nothing is needed to configure) +3. In "sources" window, add the Verilog files (*.v) to **simulation sources** +4. Run simulation (run until stops) +5. Watch the value of signal `success` or check the output message in "Tcl Console" + +### Using Icarus Verilog +1. Installing iverilog and gtkwave +``` +sudo apt-get install iverilog gtkwave +``` + +2. Compilation +Note: Zynq 7000 FPGA primitives (FDCE, LUT, ...) are not supported by iverilog, so behavioral models for these components are provided for simulation purposes. +``` +iverilog -s EzLogic_tb -o EzLogic.vvp ./problem/EzLogic_top_synth.v ./problem/EzLogic_tb.v ./behavioral\ models/*.v +``` +If successful, you can see `EzLogic.vvp` file in the folder. + +3. Running the Simulation +``` +vvp EzLogic.vvp +``` +The results of the check are printed on the terminal. + +4. Viewing in Graph Form +If you want to check internal signals, just use gtkwave. +``` +gtkwave EzLogic.vcd +``` + +## Hints +- A schematic printout is included in `schematic` folder, which can greatly assist you in understanding the data pathways and program logic. (Only for EzLogic) +- Variable names are auto-generated by Vivado Synthesizer and don't necessarily mean anything; don't be confused by the names. diff --git a/0ctf/EzLogic/schematic/schematic.pdf b/0ctf/EzLogic/schematic/schematic.pdf new file mode 100644 index 0000000..bed1c96 --- /dev/null +++ b/0ctf/EzLogic/schematic/schematic.pdf @@ -0,0 +1,6257 @@ +%PDF-1.4 +1 0 obj +<< + /Title (Logic_Basic) + /Author (13573) + /Producer (Concept Engineering GmbH) + /Creator (Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36) + /CreationDate (D:20240901110701) +>> +endobj +2 0 obj +<< + /Type /Catalog + /Pages 3 0 R + /Outlines 7 0 R + /PageMode /UseThumbs + /ViewerPreferences << /DisplayDocTitle true >> +>> +endobj +4 0 obj +<< + /Type /Font + /Subtype /Type1 + /Name /F1 + /BaseFont /Helvetica + /Encoding /MacRomanEncoding +>> +endobj +5 0 obj +<< + /ExtGState 6 0 R + /Font << /F1 4 0 R >> + /ColorSpace << /PCS [/Pattern /DeviceRGB] >> + /Pattern 8 0 R + /XObject 9 0 R +>> +endobj +% +% Nlview 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Td +(valid_in) Tj +ET +Q +0 640 m +-7 647 l +-21 647 l +-21 633 l +-7 633 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 -25 640 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-26.676 -4.308 Td +(rst_n) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +40 500 m +40 488 l +70 500 l +40 512 l +h f +Q +40 500 m +40 488 l +70 500 l +40 512 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 42 486 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(clk_IBUF_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 42 514 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +80 500 m +70 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 72 499 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +30 500 m +40 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 38 499 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +40 640 m +40 628 l +70 640 l +40 652 l +h f +Q +40 640 m +40 628 l +70 640 l +40 652 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 42 626 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(rst_n_IBUF_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 42 654 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +80 640 m +70 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 72 639 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +30 640 m +40 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 38 639 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +210 500 m +210 488 l +240 500 l +210 512 l +h f +Q +210 500 m +210 488 l +240 500 l +210 512 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 212 486 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(clk_IBUF_BUFG_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 212 514 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(BUFG) Tj +ET +Q +250 500 m +240 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 499 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +200 500 m +210 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 208 499 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +210 570 m +210 558 l +240 570 l +210 582 l +h f +Q +210 570 m +210 558 l +240 570 l +210 582 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 212 556 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(valid_in_IBUF_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 212 584 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +250 570 m +240 570 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 242 569 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +200 570 m +210 570 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 208 569 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +210 630 60 20 re +f +Q +210 630 60 20 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 240 628 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[7]_i_2) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 240 652 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT1) Tj +ET +Q +280 640 m +270 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 268 640 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +200 640 m +210 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 212 640 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +500 200 m +500 188 l +530 200 l +500 212 l +h f +Q +500 200 m +500 188 l +530 200 l +500 212 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 186 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_in_IBUF[4]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 214 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +540 200 m +530 200 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 532 199 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +490 200 m +500 200 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 498 199 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +500 270 m +500 258 l +530 270 l +500 282 l +h f +Q +500 270 m +500 258 l +530 270 l +500 282 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 256 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_in_IBUF[5]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 284 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +540 270 m +530 270 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 532 269 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +490 270 m +500 270 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 498 269 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +500 340 m +500 328 l +530 340 l +500 352 l +h f +Q +500 340 m +500 328 l +530 340 l +500 352 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 326 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_in_IBUF[6]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 354 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +540 340 m +530 340 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 532 339 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +490 340 m +500 340 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 498 339 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +500 410 m +500 398 l +530 410 l +500 422 l +h f +Q +500 410 m +500 398 l +530 410 l +500 422 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 396 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_in_IBUF[7]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 424 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +540 410 m +530 410 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 532 409 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +490 410 m +500 410 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 498 409 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +500 480 70 100 re +f +Q +500 480 70 100 re +S +500 503 m +507 500 l +500 497 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 535 478 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-42.36 2.484 Td +(data_reg_reg[7]) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 535 582 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +580 530 m +570 530 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 568 530 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +490 500 m +500 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 509 500 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +490 520 m +500 520 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 520 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +490 540 m +500 540 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 540 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +490 560 m +500 560 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 502 560 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +820 100 60 40 re +f +Q +820 100 60 40 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 850 98 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[7]_i_3) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 850 142 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT2) Tj +ET +Q +890 110 m +880 110 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 878 110 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +810 110 m +820 110 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 822 110 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +810 130 m +820 130 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 822 130 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I1) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +820 190 60 40 re +f +Q +820 190 60 40 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 850 188 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[7]_i_4) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 850 232 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT2) Tj +ET +Q +890 200 m +880 200 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 878 200 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +810 200 m +820 200 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 822 200 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +810 220 m +820 220 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 822 220 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I1) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +820 280 60 40 re +f +Q +820 280 60 40 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 850 278 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[7]_i_5) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 850 322 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT2) Tj +ET +Q +890 290 m +880 290 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 878 290 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +810 290 m +820 290 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 822 290 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +810 310 m +820 310 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 822 310 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I1) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +820 380 60 40 re +f +Q +820 380 60 40 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 850 378 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[7]_i_6) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 850 422 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT2) Tj +ET +Q +890 390 m +880 390 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 878 390 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +810 390 m +820 390 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 822 390 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +810 410 m +820 410 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 822 410 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I1) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1050 430 120 80 re +f +Q +1050 430 120 80 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1110 428 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-53.7 2.484 Td +(data_reg_reg[7]_i_1) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1110 512 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-24.336 -8.616 Td +(CARRY4) Tj +ET +Q +1040 440 m +1050 440 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1052 440 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CI) Tj +ET +Q +1040 460 m +1050 460 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1052 460 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CYINIT) Tj +ET +Q +3 w +1180 460 m +1170 460 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1168 460 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-34.46 -3.59 Td +(CO[3:0]) Tj +ET +Q +1180 480 m +1170 480 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1168 480 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-27.24 -3.59 Td +(O[3:0]) Tj +ET +Q +1040 480 m +1050 480 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1052 480 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(DI[3:0]) Tj +ET +Q +1040 500 m +1050 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1052 500 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S[3:0]) Tj +ET +Q +1 w +1002 540 m +1018 540 l +S +1005 543 m +1015 543 l +S +1008 546 m +1012 546 l +S +q +1.000 1.000 0.800 rg +/GSa0 gs +1340 230 m +1340 218 l +1370 230 l +1340 242 l +h f +Q +1340 230 m +1340 218 l +1370 230 l +1340 242 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 216 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_in_IBUF[0]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 244 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +1380 230 m +1370 230 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1372 229 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +1330 230 m +1340 230 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1338 229 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1340 310 m +1340 298 l +1370 310 l +1340 322 l +h f +Q +1340 310 m +1340 298 l +1370 310 l +1340 322 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 296 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_in_IBUF[1]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 324 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +1380 310 m +1370 310 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1372 309 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +1330 310 m +1340 310 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1338 309 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1340 380 m +1340 368 l +1370 380 l +1340 392 l +h f +Q +1340 380 m +1340 368 l +1370 380 l +1340 392 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 366 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_in_IBUF[2]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 394 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +1380 380 m +1370 380 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1372 379 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +1330 380 m +1340 380 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1338 379 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1340 450 m +1340 438 l +1370 450 l +1340 462 l +h f +Q +1340 450 m +1340 438 l +1370 450 l +1340 462 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 436 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_in_IBUF[3]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 464 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(IBUF) Tj +ET +Q +1380 450 m +1370 450 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1372 449 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 2.07 Td +(O) Tj +ET +Q +1330 450 m +1340 450 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1338 449 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-2.78 2.07 Td +(I) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1340 590 70 100 re +f +Q +1340 590 70 100 re +S +1340 613 m +1347 610 l +1340 607 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1375 588 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-42.36 2.484 Td +(data_reg_reg[2]) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1375 692 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +1420 640 m +1410 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1408 640 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +1330 610 m +1340 610 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1349 610 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +1330 630 m +1340 630 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 630 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +1330 650 m +1340 650 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 650 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +1330 670 m +1340 670 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 670 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1340 740 70 100 re +f +Q +1340 740 70 100 re +S +1340 763 m +1347 760 l +1340 757 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1375 738 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-42.36 2.484 Td +(data_reg_reg[4]) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1375 842 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +1420 790 m +1410 790 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1408 790 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +1330 760 m +1340 760 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1349 760 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +1330 780 m +1340 780 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 780 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +1330 800 m +1340 800 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 800 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +1330 820 m +1340 820 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 820 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1340 900 70 100 re +f +Q +1340 900 70 100 re +S +1340 923 m +1347 920 l +1340 917 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1375 898 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-42.36 2.484 Td +(data_reg_reg[5]) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1375 1002 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +1420 950 m +1410 950 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1408 950 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +1330 920 m +1340 920 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1349 920 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +1330 940 m +1340 940 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 940 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +1330 960 m +1340 960 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 960 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +1330 980 m +1340 980 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 980 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1340 1100 70 100 re +f +Q +1340 1100 70 100 re +S +1340 1123 m +1347 1120 l +1340 1117 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1375 1098 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-42.36 2.484 Td +(data_reg_reg[6]) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1375 1202 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +1420 1150 m +1410 1150 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1408 1150 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +1330 1120 m +1340 1120 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1349 1120 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +1330 1140 m +1340 1140 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 1140 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +1330 1160 m +1340 1160 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 1160 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +1330 1180 m +1340 1180 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1342 1180 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1640 200 60 40 re +f +Q +1640 200 60 40 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1670 198 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[3]_i_2) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1670 242 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT2) Tj +ET +Q +1710 210 m +1700 210 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1698 210 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +1630 210 m +1640 210 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1642 210 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +1630 230 m +1640 230 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1642 230 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I1) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1640 300 60 40 re +f +Q +1640 300 60 40 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1670 298 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[3]_i_3) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1670 342 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT2) Tj +ET +Q +1710 310 m +1700 310 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1698 310 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +1630 310 m +1640 310 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1642 310 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +1630 330 m +1640 330 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1642 330 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I1) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1640 390 60 40 re +f +Q +1640 390 60 40 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1670 388 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[3]_i_4) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1670 432 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT2) Tj +ET +Q +1710 400 m +1700 400 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1698 400 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +1630 400 m +1640 400 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1642 400 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +1630 420 m +1640 420 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1642 420 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I1) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1640 490 60 40 re +f +Q +1640 490 60 40 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1670 488 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-41.694 2.484 Td +(data_reg[3]_i_5) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1670 532 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-14.67 -8.616 Td +(LUT2) Tj +ET +Q +1710 500 m +1700 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1698 500 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(O) Tj +ET +Q +1630 500 m +1640 500 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1642 500 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I0) Tj +ET +Q +1630 520 m +1640 520 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1642 520 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(I1) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +1830 590 120 80 re +f +Q +1830 590 120 80 re +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1890 588 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-53.7 2.484 Td +(data_reg_reg[3]_i_1) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1890 672 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-24.336 -8.616 Td +(CARRY4) Tj +ET +Q +1820 600 m +1830 600 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1832 600 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CI) Tj +ET +Q +1820 620 m +1830 620 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1832 620 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CYINIT) Tj +ET +Q +3 w +1960 620 m +1950 620 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1948 620 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-34.46 -3.59 Td +(CO[3:0]) Tj +ET +Q +1960 640 m +1950 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1948 640 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-27.24 -3.59 Td +(O[3:0]) Tj +ET +Q +1820 640 m +1830 640 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1832 640 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(DI[3:0]) Tj +ET +Q +1820 660 m +1830 660 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 1832 660 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(S[3:0]) Tj +ET +Q +1 w +1782 700 m +1798 700 l +S +1785 703 m +1795 703 l +S +1788 706 m +1792 706 l +S +q +1.000 1.000 0.800 rg +/GSa0 gs +2140 530 70 100 re +f +Q +2140 530 70 100 re +S +2140 553 m +2147 550 l +2140 547 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2175 528 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-42.36 2.484 Td +(data_reg_reg[0]) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2175 632 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +2220 580 m +2210 580 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2208 580 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +2130 550 m +2140 550 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2149 550 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +2130 570 m +2140 570 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 570 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +2130 590 m +2140 590 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 590 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +2130 610 m +2140 610 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 610 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +2140 680 70 100 re +f +Q +2140 680 70 100 re +S +2140 703 m +2147 700 l +2140 697 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2175 678 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-42.36 2.484 Td +(data_reg_reg[1]) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2175 782 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +2220 730 m +2210 730 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2208 730 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +2130 700 m +2140 700 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2149 700 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +2130 720 m +2140 720 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 720 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +2130 740 m +2140 740 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 740 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +2130 760 m +2140 760 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 760 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +2140 830 70 100 re +f +Q +2140 830 70 100 re +S +2140 853 m +2147 850 l +2140 847 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2175 828 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-42.36 2.484 Td +(data_reg_reg[3]) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2175 932 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +2220 880 m +2210 880 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2208 880 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +2130 850 m +2140 850 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2149 850 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +2130 870 m +2140 870 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 870 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +2130 890 m +2140 890 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 890 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +2130 910 m +2140 910 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 910 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +2090 960 m +2090 956 l +S +2082 956 m +2098 956 l +S +q +1.000 1.000 0.800 rg +/GSa0 gs +2140 990 70 100 re +f +Q +2140 990 70 100 re +S +2140 1013 m +2147 1010 l +2140 1007 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2175 988 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-36.018 2.484 Td +(valid_out_reg) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2175 1092 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +-16.332 -8.616 Td +(FDCE) Tj +ET +Q +2220 1040 m +2210 1040 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2208 1040 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +-7.78 -3.59 Td +(Q) Tj +ET +Q +2130 1010 m +2140 1010 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2149 1010 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(C) Tj +ET +Q +2130 1030 m +2140 1030 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 1030 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CE) Tj +ET +Q +2130 1050 m +2140 1050 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 1050 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(CLR) Tj +ET +Q +2130 1070 m +2140 1070 l +S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2142 1070 cm +BT +/F1 10 Tf +1 0 0 -1 0 0 Tm +0 -3.59 Td +(D) Tj +ET +Q +q +1.000 1.000 0.800 rg +/GSa0 gs +2340 40 m +2340 28 l +2370 40 l +2340 52 l +h f +Q +2340 40 m +2340 28 l +2370 40 l +2340 52 l +h S +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2342 26 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 2.484 Td +(data_out_OBUF[0]_inst) Tj +ET +Q +q +0.000 0.000 0.000 rg +/GSa0 gs +1 0 0 1 2342 54 cm +BT +/F1 12 Tf +1 0 0 -1 0 0 Tm +0 -8.616 Td +(OBUF) Tj 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